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EM78P568
8-bit OTP Micro-controller
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* This specification are subject to be changed without notice.
01/31/2004 V4.7
VII.3 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
CONT (Control Register)
7
6
P70EG
INT
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit 3(PAB) : Prescaler assignment bit
0/1
TCC/WDT
Bit 4(RETBK) : Return value backup control for interrupt routine
0
disable/enable
When this bit is set to 1, the CPU will store ACC,R3 status and R5 PAGE automatically after an interrupt is
triggered. And it will be restored after instruction RETI. When this bit is set to 0, the user need to store ACC,
R3 and R5 PAGE in user program.
Bit 5(TS) : TCC signal source
0
internal instruction cycle clock
1
16.384kHz
Bit 6 (INT) : INT enable flag
0
interrupt masked by DISI or hardware interrupt
1
interrupt enabled by ENI/RETI instructions
Bit 7(P70EG) : interrupt edge type of P70
0
P70 's interruption source is a rising edge signal.
1
P70 's interruption source is a falling edge signal.
CONT register is readable (CONTR) and writable (CONTW).
TCC and WDT :
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC
only or WDT only at the same time.
An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT
register.
See the prescaler ratio in CONT register.
Fig.17 depicts the circuit diagram of TCC/WDT.
Both TCC and prescaler will be cleared by instructions which write to TCC each time.
The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
5
TS
4
3
2
1
0
RETBK
PAB
PSR2
PSR1
PSR0
PSR0
0
1
0
1
0
1
0
1
TCC rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128