參數(shù)資料
型號(hào)： EM78P568
廠商： ELAN Microelctronics Corp .
英文描述： 8-BIT OTP MICRO-CONTROLLER
中文描述： 8位檢察官微控制器
文件頁(yè)數(shù)： 24/61頁(yè)
文件大?。?/td> 568K
代理商： EM78P568
EM78P568
8-bit OTP Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
01/31/2004 V4.7
01010001
01001110
173.8
179.9
183.5
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
81
78
76
75
74
73
71
70
69
68
66
64
62
61
60
58
56
55
172.773
179.419
184.140
186.595
189.117
191.708
197.108
199.924
202.821
205.804
212.040
218.667
225.720
229.421
233.244
241.287
249.905
254.448
01001011
01001010
01001001
01000111
01000110
01000101
01000100
01000010
01000000
00111110
00111101
00111100
00111010
00111000
00110111
RF (Interrupt status)
(Interrupt status register)
7
INT3
R/W-0
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF) : TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1(CNT1) : counter1 timer overflow interrupt flag
Set when counter1 timer overflows.
Bit 2(CNT2) : counter2 timer overflow interrupt flag
Set when counter2 timer overflows.
Bit 3(INT0) : external INT0 pin interrupt flag
If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit.
Bit 4(INT1) : external INT1 pin interrupt flag
If PORT71 has a falling edge trigger signal, CPU will set this bit.
Bit 5(INT2) : external INT2 pin interrupt flag
If PORT72 has a falling edge trigger signal, CPU will set this bit.
Bit 6(DETO) : CTCSS tone detection interrupt flag
If CTCSS detection output signal(R7 PAGE1 bit 6) has an edge signal (falling edge, falling and rising
edge), CPU will set this bit.
Bit 7(INT3) : external INT3 pin interrupt flag
If PORT73 has a falling edge trigger signal, CPU will set this bit.
<Note> IOCF is the interrupt mask register. User can read and clear.
6
5
4
3
2
1
0
DETO
R/W-0
INT2
R/W-0
INT1
R/W-0
INT0
R/W-0
CNT2
R/W-0
CNT1
R/W-0
TCIF
R/W-0
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