參數(shù)資料
型號： ENC424J600T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 154/168頁
文件大小： 0K
描述： IC ETHERNET CTRLR W/SPI 44-QFN
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,600
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 44-QFN（8x8）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
PIC18F2220/2320/4220/4320
DS39599G-page 84
2007 Microchip Technology Inc.
7.7
Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write opera-
tions are disabled if either of these mechanisms are
enabled.
The microcontroller itself can both read and write to the
internal Data EEPROM regardless of the state of the
code-protect Configuration bit. Refer to Section 23.0
information.
7.8
Using the Data EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124 or D124A. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
EXAMPLE 7-3:
DATA EEPROM REFRESH ROUTINE
TABLE 7-1:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Note:
If data EEPROM is only used to store
constants and/or data that changes rarely,
an array refresh is likely not required. See
specification D124 or D124A.
CLRF
EEADR
; Start at address 0
BCF
EECON1, CFGS
; Set for memory
BCF
EECON1, EEPGD
; Set for Data EEPROM
BCF
INTCON, GIE
; Disable interrupts
BSF
EECON1, WREN
; Enable writes
LOOP
; Loop to refresh array
BSF
EECON1, RD
; Read current address
MOVLW
55h
;
MOVWF
EECON2
; Write 55h
MOVLW
AAh
;
MOVWF
EECON2
; Write AAh
BSF
EECON1, WR
; Set WR bit to begin write
BTFSC
EECON1, WR
; Wait for write to complete
BRA
$-2
INCFSZ EEADR, F
; Increment address
BRA
Loop
; Not zero, do it again
BCF
EECON1, WREN
; Disable writes
BSF
INTCON, GIE
; Enable interrupts
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
EEADR
EEPROM Address Register
0000 0000 0000 0000
EEDATA
EEPROM Data Register
0000 0000 0000 0000
EECON2
EEPROM Control Register 2 (not a physical register)
—
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 uu-0 u000
IPR2
OSCFIP
CMIP
—EEIP
BCLIP
LVDIP
TMR3IP
CCP2IP 11-1 1111 ---1 1111
PIR2
OSCFIF
CMIF
—EEIF
BCLIF
LVDIF
TMR3IF
CCP2IF 00-0 0000 ---0 0000
PIE2
OSCFIE
CMIE
—EEIE
BCLIE
LVDIE
TMR3IE
CCP2IE 00-0 0000 ---0 0000
Legend:
x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’.
Shaded cells are not used during Flash/EEPROM access.
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