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參數(shù)資料
型號： ENC424J600T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 24/168頁
文件大?。?/td> 0K
描述： IC ETHERNET CTRLR W/SPI 44-QFN
視頻文件： Fast 100 Mbps Ethernet PICtail Plus Overview
標(biāo)準(zhǔn)包裝： 1,600
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： SPI
電源電壓： 3 V ~ 3.6 V
電流 - 電源： 96mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 44-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 44-QFN（8x8）
包裝： 帶卷 (TR)
配用： AC164132-ND - BOARD DAUGHTER PICTAIL ETHERNET
ENC424J600/624J600
DS39935C-page 10
2010 Microchip Technology Inc.
2.3
Voltage and Bias Pin
2.3.1
VDD AND VSS PINS
To reduce on-die noise levels and provide for the
high-current demands of Ethernet, there are many
power pins on ENC424J600/624J600 devices:
VDD and VSS
VDDOSC and VSSOSC
VDDPLL and VSSPLL
VDDRX and VSSRX
VDDTX and VSSTX
Each VDD and VSS pin pair above should have a 0.1
F
ceramic bypass capacitor placed as close to the pins as
possible. For best EMI emission suppression, other
smaller capacitors, such as 0.001
F, should be placed
immediately across VDDTX/VSSTX and VDDPLL/VSSPLL.
All VDD power supply pins must be externally con-
nected to the same 3.3V ±10% power source. Similarly,
all VSS supply references must be externally connected
to the same ground node. If a ground connection
appears on two pins (e.g., VSSTX), connect both pins;
do not allow either to float. In addition, it is
recommended that the exposed bottom metal pad on
the 44-pin QFN package be tied to VSS.
Placing ferrite beads or inductors between any two of
the supply pins (e.g., between VDDOSC and VDDRX) is
not recommended. However, it is acceptable to isolate
all of the VDD supplies from the main circuit power sup-
ply through a single ferrite bead or inductor, if desired
for supply noise suppression reasons. Such isolation is
generally not necessary.
2.3.2
VCAP PIN
Most of the device’s digital logic operates at a nominal
1.8V. This voltage is supplied by an on-chip voltage
regulator, which generates the digital supply voltage
from the VDD rail. The only external component
required is an external filter capacitor, connected from
the VCAP pin to ground, as shown in Figure 2-3. A value
of at least 10
F is recommended.
The capacitor must also have a relatively low Equiva-
lent Series Resistance (ESR). It is recommended that
a low-ESR capacitor (ceramic, tantalum or similar)
should be used and high-ESR capacitors (such as
aluminum electrolytic) should be avoided.
The internal regulator is not designed to drive external
loads; therefore, do not attach other circuitry to VCAP.
FIGURE 2-3:
VCAP CONNECTIONS
2.3.3
RBIAS PIN
The internal analog circuitry in the PHY module
requires that an external 12.4 k, 1% resistor be
attached from RBIAS to ground, as shown in
Figure 2-4. The resistor influences the TPOUT+/-
signal amplitude. The RBIAS resistor should be placed
as close as possible to the chip with no immediately
adjacent signal traces in order to prevent noise
capacitively coupling into the pin and affecting the
transmit behavior. It is recommended that the resistor
be a surface mount type.
FIGURE 2-4:
RBIAS RESISTOR
VDD
VCAP
VSS
ENCX24J600
10
F
3.3V
0.1
F
Regulator
+3.3V
I/O, PHY
+1.8V
Core, RAM,
MAC
RBIAS
ENCX24J600
12.4
k1%
PHY
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