參數(shù)資料
型號: EPM7032BLC44-3
廠商: Altera
文件頁數(shù): 1/66頁
文件大小: 0K
描述: IC MAX 7000 CPLD 32 44-PLCC
標準包裝: 130
系列: MAX® 7000B
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 3.5ns
電壓電源 - 內部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
Altera Corporation
1
MAX 7000B
Programmable Logic
Device
September 2005, ver. 3.5
Data Sheet
DS-MAX7000B-3.5
Features...
High-performance 2.5-V CMOS EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX) architecture (see Table 1)
Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V
MAX 7000A device families
High-density PLDs ranging from 600 to 10,000 usable gates
3.5-ns pin-to-pin logic delays with counter frequencies in excess
of 303.0 MHz
Advanced 2.5-V in-system programmability (ISP)
Programs through the built-in IEEE Std. 1149.1 Joint Test Action
Group (JTAG) interface with advanced pin-locking capability
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in-system programming
ISP circuitry compliant with IEEE Std. 1532
f For information on in-system programmable 5.0-V MAX 7000S or 3.3-V
Table 1. MAX 7000B Device Features
Feature
EPM7032B
EPM7064B
EPM7128B
EPM7256B
EPM7512B
Usable gates
600
1,250
2,500
5,000
10,000
Macrocells
32
64
128
256
512
Logic array blocks
2
4
8
16
32
Maximum user I/O
pins
36
68
100
164
212
tPD (ns)
3.5
4.0
5.0
5.5
tSU (ns)
2.1
2.5
3.3
3.6
tFSU (ns)
1.0
tCO1 (ns)
2.4
2.8
3.3
3.7
fCNT (MHz)
303.0
243.9
188.7
163.9
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