Note: (1) EPM7032B, EPM7064B, EPM7" />
參數(shù)資料
型號: EPM7032BLC44-3
廠商: Altera
文件頁數(shù): 56/66頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 32 44-PLCC
標(biāo)準(zhǔn)包裝: 130
系列: MAX® 7000B
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 3.5ns
電壓電源 - 內(nèi)部: 2.375 V ~ 2.625 V
邏輯元件/邏輯塊數(shù)目: 2
宏單元數(shù): 32
門數(shù): 600
輸入/輸出數(shù): 36
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.58x16.58)
包裝: 管件
6
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Figure 1. MAX 7000B Device Block Diagram
Note:
(1)
EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten
output enables.
Logic Array Blocks
The MAX 7000B device architecture is based on the linking of
high-performance LABs. LABs consist of 16 macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
36 signals from the PIA that are used for general logic inputs
Global controls that are used for secondary register functions
Direct input paths from I/O pins to the registers that are used for fast
setup times
6 or 10
INPUT/GCLRn
6 or 10 Output Enables
(1)
6 or 10 Output Enables
(1)
16
36
16
I/O
Control
Block
LAB C
LAB D
I/O
Control
Block
6 or 10
16
36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6 or 10
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
2 to 16 I/O
2 to 16
Macrocells
17 to 32
Macrocells
33 to 48
Macrocells
49 to 64
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