參數(shù)資料
型號: EPM7064AETI44-7N
廠商: Altera
文件頁數(shù): 5/64頁
文件大?。?/td> 0K
描述: IC MAX 7000 CPLD 64 44-TQFP
產(chǎn)品變化通告: Bond Wire Change 4/Sept/2008
標準包裝: 480
系列: MAX® 7000A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 4
宏單元數(shù): 64
門數(shù): 1250
輸入/輸出數(shù): 36
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 604 (CN2011-ZH PDF)
其它名稱: 544-2011
EPM7064AETI44-7N-ND
Altera Corporation
13
MAX 7000A Programmable Logic Device Data Sheet
Figure 5. MAX 7000A PIA Routing
While the routing delays of channel-based routing schemes in masked or
FPGAs are cumulative, variable, and path-dependent, the MAX 7000A
PIA has a predictable delay. The PIA makes a design’s timing
performance easy to predict.
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is individually controlled by one of the global output enable
signals or directly connected to ground or VCC. Figure 6 shows the I/O
control block for MAX 7000A devices. The I/O control block has 6 or
10 global output enable signals that are driven by the true or complement
of two output enable signals, a subset of the I/O pins, or a subset of the
I/O macrocells.
To LAB
PIA Signals
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