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參數(shù)資料
| 型號(hào)： | EVAL-AD7719EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7719 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16，24 |
| 采樣率（每秒）： | 105 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 4.85mW @ 105SPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7719 |
| 已供物品： | 板 |
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REV. A
AD7719
–24–
7
R
F6
R
F5
R
F4
R
F3
R
F2
R
F1
R
F0
R
F
)
0
(
7
F
S6
F
S)
1
(5
F
S)
0
(4
F
S)
0
(3
F
S)
0
()
1
(
2
F
S)
0
(
1
F
S)
1
(
0
F
S
5
1
N
O
C
O
I4
1
N
O
C
O
I3
1
N
O
C
O
I2
1
N
O
C
O
I1
1
N
O
C
O
I0
1
N
O
C
O
I9
N
O
C
O
I8
N
O
C
O
I
)
0
(
2
W
S
P1
W
S
P)
0
(0
)
0
(O
B)
0
(N
I
P
2
I)
0
()
1
(
N
I
P
1
I)
0
(
N
E
2
I)
0
(
N
E
1
I
7
N
O
C
O
I6
N
O
C
O
I5
N
O
C
O
I4
N
O
C
O
I3
N
O
C
O
I2
N
O
C
O
I1
N
O
C
O
I0
N
O
C
O
I
)
0
(
R
I
D
4
P)
0
(
R
I
D
3
P)
0
(
N
E
2
P)
0
(
N
E
1
P)
0
(
T
A
D
4
P)
0
(
T
A
D
3
P)
0
(
T
A
D
2
P)
0
(
T
A
D
1
P
Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On
Reset = 0x45)
The Filter register is an 8-bit register from which data can be
read or to which data can be written. This register determines
the amount of averaging performed by the sinc filter. Table XV
outlines the bit designations for the Filter register. FR7 through
FR0 indicate the bit location, with FR denoting that the bits are in
the Filter register. FR7 denotes the first bit of the data stream.
The number in parentheses indicates the power-on/reset default
status of that bit. The number in this register is used to set the
decimation factor and thus the output update rate for the main
and aux ADCs. The filter register cannot be written to by the
user while either ADC is active. The update rate is used for both
main and aux ADCs and is calculated as follows:
f
SF
f
ADC
MOD
=×
×
1
3
1
8
where:
fADC = ADC output update rate
fMOD =Modulator clock frequency = 32.768 kHz
(main and aux ADC)
SF
=Decimal value written to SF register
The allowable range for SF is 13dec to 255dec. Examples of SF
values and corresponding conversion rate (fADC) and time (tADC)
are shown in Table XV. It should also be noted that both ADC
input channels are chopped to minimize offset errors. This
means that the time for a single conversion or the time to the
first conversion result is 2
× t
ADC.
Table XV. Update Rate vs. SF WORD
SF (dec)
SF (Hex)
fADC (Hz)
tADC (ms)
13
0D
105.3
9.52
69
45
19.79
50.34
255
FF
5.35
186.77
I/O and Current Source Control Register (IOCON): (A3, A2,
A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000)
The IOCON register is a 16-bit register from which data can be
read or to which data can be written. This register is used to control
and configure the various excitation and burnout current source
options available on-chip along with controlling the I/O port.
Table XVI outlines the bit designations for this register. IOCON15
through IOCON0 indicate the bit location, with IOCON denoting
that the bits are in the I/O and Current Source control register.
IOCON15 denotes the first bit of the data stream. The number
in parentheses indicates the power-on/reset default status of that
bit. A write to the IOCON register has immediate effect and
does not reset the ADCs. Thus if a current source is switched
while the ADC is converting, the user will have to wait for the
full settling time of the filter before getting a fully settled output.
Since the ADC is chopped, this equates to three outputs.
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