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參數(shù)資料
| 型號： | EVAL-AD7719EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7719 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16，24 |
| 采樣率（每秒）： | 105 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標準）： | 4.85mW @ 105SPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7719 |
| 已供物品： | 板 |
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REV. A
AD7719
–10–
PIN FUNCTION DESCRIPTIONS (continued)
Pin No.
Mnemonic
Function
16
P2/SW2
Dual-Purpose Pin. It can act as a general-purpose output (P2) bit referenced between AVDD and AGND
or as a low-side power switch (SW2) to PWRGND.
17
PWRGND
Ground Point for the Low-Side Power Switches SW2 and SW1. PWRGND must be tied to AGND.
18
P1/SW1
Dual-Purpose Pin. It can act as a general-purpose output (P1) bit referenced between AVDD and AGND
or as a low-side power switch (SW1) to PWRGND.
19
RESET
Digital Input Used to Reset the ADC to Its Power-On Reset Status. This pin has a weak pull-up internally
to DVDD.
20
SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input,
making the interface suitable for opto-isolated applications. The serial clock can be continuous with all
data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the AD7719 in smaller batches of data. A weak pull-up to DVDD
is provided on the SCLK input.
21
CS
Chip Select Input. This is an active low logic input used to select the AD7719.
CS can be used to select
the AD7719 in systems with more than one device on the serial bus or as a frame synchronization signal in
communicating with the device.
CS can be hardwired low, allowing the AD7719 to be operated in 3-wire
mode with SCLK, DIN, and DOUT used to interface with the device. A weak pull-up to DVDD is provided
on the CS input.
22
RDY
RDY is a logic low status output from the AD7719. RDY is low if either the main ADC or auxiliary ADC
channel has valid data in its data register. This output returns high on completion of a read operation
from the data register. If data is not read,
RDY will return high prior to the next update, indicating to the
user that a read operation should not be initiated. The
RDY pin also returns low following the completion
of a calibration cycle. The
RDY pin is effectively the digital NOR function of the RDY0 and RDY1 bits in
the Status register. If one of the ADCs is disabled, the
RDY pin reflects the active ADC. RDY does not
return high after a calibration until the mode bits are written to, enabling a new conversion or calibration.
Since the
RDY pin provides information on both the main and aux ADCs, when either the main or aux
ADC is disabled, it is recommended to immediately read its data register to ensure that its RDY bit goes
inactive and releases the
RDY pin to indicate output data updates on the remaining active ADC.
23
DOUT
Serial Data Output Accessing the Output Shift Register of the AD7719. The output shift register can
contain data from any of the on-chip data, calibration, or control registers.
24
DIN
Serial Data Input Accessing the Input Shift Register on the AD7719. Data in this shift register is transferred
to the calibration or control registers within the ADC depending on the selection bits of the Communications
register. A weak pull-up to DVDD is provided on the DIN input.
25
DGND
Ground Reference Point for the Digital Circuitry.
26
DVDD
Digital Supply Voltage, 3 V or 5 V Nominal.
27
XTAL2
Output from the 32 kHz Crystal Oscillator Inverter.
28
XTAL1
Input to the 32 kHz Crystal Oscillator Inverter.
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