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參數(shù)資料
| 型號： | EVAL-AD7719EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD7719 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16，24 |
| 采樣率（每秒）： | 105 |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 4.85mW @ 105SPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7719 |
| 已供物品： | 板 |
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REV. A
AD7719
–12–
DUAL-CHANNEL ADC CIRCUIT INFORMATION
Overview
The AD7719 incorporates two independent
Σ- ADC channels
(main and auxiliary) with on-chip digital filtering intended for
the measurement of wide dynamic range, low frequency signals
such as those in weigh-scale, strain gage, pressure transducer, or
temperature measurement applications.
Main Channel
This channel is intended to convert the primary sensor input.
This channel can be operated in buffered or unbuffered mode, and
can be programmed to have one of eight input voltage ranges
from ±20 mV to ±2.56 V. This channel can be configured as
either two fully differential inputs (AIN1/AIN2 and AIN3/AIN4)
or three pseudodifferential input channels (AIN1/AIN4, AIN2/
AIN4, and AIN3/AIN4). Buffering the input channel means that
the part can accommodate significant source impedances on the
analog input and that R, C filtering (for noise rejection or RFI
reduction) can be placed on the analog inputs if required. Operat-
ing in unbuffered mode leads to lower power consumption in low
power applications, but care must be exercised in unbuffered mode
because source impedances can introduce gain errors. The main
ADC also features sensor burnout currents that can be switched
on and off. These currents can be used to check that a transducer
is still operational before attempting to take measurements.
The ADC employs a
Σ- conversion technique to realize up to
24 bits of no-missing-codes performance. The
Σ- modulator
converts the sampled input signal into a digital pulse train whose
duty cycle contains the digital information. A Sinc
3 programmable
low-pass filter is then employed to decimate the modulator output
data stream to give a valid data conversion result at program-
mable output rates from 5.35 Hz (186.77 ms) to 105.03 Hz
(9.52 ms). A chopping scheme is also employed to minimize
ADC channel offset errors. A block diagram of the main ADC
input channel is shown in Figure 4. The sampling frequency of
the modulator loop is many times higher than the bandwidth of
the input signal. The integrator in the modulator shapes the
quantization noise (which results from the analog-to-digital
conversion) so that the noise is pushed toward one-half of the
modulator frequency. The output of the
Σ- modulator feeds
directly into the digital filter. The digital filter then band-limits
the response to a frequency significantly lower than one-half of
the modulator frequency. In this manner, the 1-bit output of the
comparator is translated into a band-limited, low noise output
from the AD7719 ADC. The AD7719 filter is a low-pass, Sinc
3,
or (SIN(x)/x)
3 filter whose primary function is to remove the
quantization noise introduced at the modulator. The cutoff
frequency and decimated output data rate of the filter are pro-
grammable via the SF word loaded to the filter register.
A chopping scheme is employed where the complete signal chain is
chopped, resulting in excellent dc offset and offset drift specifi-
cations, and is extremely beneficial in applications where drift, noise
rejection, and optimum EMI rejection are important factors.
With chopping, the ADC repeatedly reverses its inputs. The
decimated digital output words from the Sinc
3 filters therefore
have a positive offset and negative offset term included. As a result,
a final summing stage is included so that each output word from
the filter is summed and averaged with the previous filter output
to produce a new valid output result to be written to the ADC
data register.
Auxiliary Channel
The Auxiliary (Aux) channel is intended to convert supplementary
inputs such as those from a cold junction diode or thermistor.
This channel is unbuffered and has an input range of ±REFIN2
or ±REFIN2/2, determined by the ARN bit in the auxiliary ADC
control register (AD1CON). AIN3 and AIN4 can be multiplexed
into the auxiliary channel as single-ended inputs with respect to
AGND, while AIN5 and AIN6 can operate as a differential
input pair. With AIN6 tied to AGND, AIN5 can be operated as
an additional single-ended input. A block diagram of the auxiliary
ADC channel is shown in Figure 5.
SINC3 FILTER
MUX
BUF
PGA
MOD0
XOR
ANALOG
INPUT
DIGITAL
OUTPUT
1
8
SF
3
(
)
(8
SF )
3
1
2
AIN + VOS
AIN – VOS
f
CHOP
f
IN
f
MOD
f
CHOP
f
ADC
-
Figure 4. Main ADC Channel Block Diagram
OSCILLATOR
AVDD = DVDD = 5V
TA = 25 C
TIME BASE = 100ms/DIV
TRACE 1 = TRACE 2 = 2V/DIV
VDD
TPC 7. Typical Oscillator Power-Up
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