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| 型號(hào)： | EVAL-ADUC812QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR ADUC812 |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC812 |
| 所含物品： | 評(píng)估板、電源、纜線、軟件和說明文檔 |
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REV.
ADuC812
–26–
MOSI (Master Out, Slave In Pin)
The MOSI (master out, slave in) pin is configured as an output
line in master mode and an input line in slave mode. The
MOSI line on the master (data out) should be connected to the
MOSI line in the slave device (data in). The data is transferred as
byte wide (8-bit) serial data, MSB first.
SCLOCK (Serial Clock I/O Pin)
The master serial clock (SCLOCK) is used to synchronize the
data being transmitted and received through the MOSI and MISO
data lines. A single data bit is transmitted and received in each
SCLOCK period. Therefore, a byte is transmitted/received after
eight SCLOCK periods. The SCLOCK pin is configured as an
output in master mode and as an input in slave mode. In master
mode, the bit rate, polarity, and phase of the clock are controlled
by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR
(see Table XI). In slave mode, the SPICON register will have to
be configured with the phase and polarity (CPHA and CPOL) of
the expected input clock. In both master and slave modes, the
data is transmitted on one edge of the SCLOCK signal and
sampled on the other. It is important therefore that the CPHA
and CPOL are configured the same for the master and slave
devices.
SS (Slave Select Input Pin)
The Slave Select (
SS) input pin is shared with the ADC5 input.
To configure this pin as a digital input, the bit must be cleared,
e.g., CLR P1.5.
This line is active low. Data is only received or transmitted in
slave mode when the
SS pin is low, allowing the ADuC812 to
be used in single master, multislave SPI configurations. If
CPHA = 1, then the
SS input may be permanently pulled low.
With CPHA = 0, the
SS input must be driven low before the
first bit in a byte wide transmission or reception, and return
high again after the last bit in that byte wide transmission or
reception. In SPI Slave mode, the logic level on the external
SS
pin can be read via the SPR0 bit in the SPICON SFR. The follow-
ing SFR registers are used to control the SPI interface.
SPI Control
SPICON
Register
SFR Address
F8H
Power-On Default Value
OOH
Bit Addressable
Yes
I
P
S
IL
O
C
WE
P
SM
I
P
SL
O
P
CA
H
P
C1
R
P
S0
R
P
S
Table XI. SPICON SFR Bit Designations
Bit
Name
Description
7
ISPI
SPI Interrupt Bit.
Set by MicroConverter at the end of each SPI transfer.
Cleared directly by user code or indirectly by reading the SPIDAT SFR.
6
WCOL
Write Collision Error Bit.
Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.
Cleared by user code.
5
SPE
SPI Interface Enable Bit.
Set by user to enable the SPI interface.
Cleared by user to enable I
2C interface.
4
SPIM
SPI Master/Slave Mode Select Bit.
Set by user to enable Master mode operation (SCLOCK is an output).
Cleared by user to enable Slave mode operation (SCLOCK is an input).
3
CPOL
*
Clock Polarity Select Bit.
Set by user if SCLOCK idles high.
Cleared by user if SCLOCK idles low.
2
CPHA
*
Clock Phase Select Bit.
Set by user if leading SCLOCK edge is to transmit data.
Cleared by user if trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit rate) in Master mode as follows:
SPR1
SPR0
Selected Bit Rate
00
fOSC/4
01
fOSC/8
10
fOSC/32
11
fOSC/64
In SPI Slave mode, i.e., SPIM = 0, the logic level on the external
SS pin can be read
via the SPR0 bit.
*The CPOL and CPHA bits should both contain the same values for master and slave devices.
F
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