
REV.
ADuC812
–48–
12 MHz
Variable Clock
Parameter
Min
Max
Min
Max
Unit
EXTERNAL DATA MEMORY READ CYCLE
tRLRH
RD Pulsewidth
400
6tCK – 100
ns
tAVLL
Address Valid after ALE Low
43
tCK –40
ns
tLLAX
Address Hold after ALE Low
48
tCK –35
ns
tRLDV
RD Low to Valid Data In
252
5tCK – 165
ns
tRHDX
Data and Address Hold after
RD
00
ns
tRHDZ
Data Float after
RD
97
2tCK – 70
ns
tLLDV
ALE Low to Valid Data In
517
8tCK – 150
ns
tAVDV
Address to Valid Data In
585
9tCK – 165
ns
tLLWL
ALE Low to
RD or WR Low
200
300
3tCK –50
3tCK +50
ns
tAVWL
Address Valid to
RD or WR Low
203
4tCK – 130
ns
tRLAZ
RD Low to Address Float
0
ns
tWHLH
RD or WR High to ALE High
43
123
tCK –40
6tCK – 100
ns
MCLK
ALE (O)
PSEN (O)
RD (O)
PORT 0 (I/O)
PORT 2 (O)
tWHLH
tLLDV
tLLWL
tRLRH
tAVWL
tLLAX
tAVLL
tRLAZ
tRHDX
tRHDZ
tAVDV
A0–A7 (OUT)
DATA (IN)
A16–A23
A8–A15
tRLDV
Figure 52. External Data Memory Read Cycle
F