參數(shù)資料
型號(hào)： EVAL-ADUC812QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/57頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR ADUC812
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC812
所含物品： 評(píng)估板、電源、纜線、軟件和說(shuō)明文檔
REV.
ADuC812
–15–
Driving the ADC
The ADC incorporates a successive approximation (SAR) archi-
tecture involving a charge-sampled input stage. Figure 7 shows
the equivalent circuit of the analog input section. Each ADC
conversion is divided into two distinct phases as defined by the
position of the switches in Figure 7. During the sampling phase
(with SW1 and SW2 in the “track” position), a charge propor-
tional to the voltage on the analog input is developed across the
input sampling capacitor. During the conversion phase (with
both switches in the “hold” position), the capacitor DAC is
adjusted via internal SAR logic until the voltage on node A is zero,
indicating that the sampled charge on the input capacitor is
balanced out by the charge being output by the capacitor DAC.
The digital value finally contained in the SAR is then latched
out as the result of the ADC conversion. Control of the SAR,
and timing of acquisition and sampling modes, is handled
automatically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.
ADuC812
TEMPERATURE
SENSOR
ADC0
ADC7
200
SW1
2pF
NODE A
COMPARATOR
SW2
HOLD
TRACK
HOLD
CAPACITOR
DAC
AGND
Figure 7. Internal ADC Structure
Note that whenever a new input channel is selected, a residual
charge from the 2 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches click
into “hold” mode. Delays can be inserted in software (between
channel selection and conversion request) to account for input
stage settling, but a hardware solution will alleviate this burden
from the software design task and will ultimately result in a
cleaner system implementation. One hardware solution would
be to choose a very fast settling op amp to drive each analog
input. Such an op amp would need to settle fully from a small
signal transient in less than 300 ns to guarantee adequate settling
under all software configurations. A better solution, recommended
for use with any amplifier, is shown in Figure 8.
Though at first glance the circuit in Figure 8 may look like a
simple antialiasing filter, it actually serves no such purpose since
its corner frequency is well above the Nyquist frequency, even at
a 200 kHz sample rate. Though the R/C does help to reject some
incoming high frequency noise, its primary function is to ensure
that the transient demands of the ADC input stage are met. It
does so by providing a capacitive bank from which the 2 pF
ADuC812
ADC0
1
0.01 F
51
Figure 8. Buffering Analog Inputs
sampling capacitor can draw its charge. Since the 0.01 μF capacitor
in Figure 8 is more than 4096 times the size of the 2 pF sampling
capacitor, its voltage will not change by more than one count
(1/4096) of the 12-bit transfer function when the 2 pF charge
from a previous channel is dumped onto it. A larger capacitor
can be used if desired, but not a larger resistor (for reasons
described below).
The Schottky diodes in Figure 8 may be necessary to limit the
voltage applied to the analog input pin as per the Absolute Maxi-
mum Ratings. They are not necessary if the op amp is powered
from the same supply as the ADuC812 since in that case, the
op amp is unable to generate voltages above VDD or below ground.
An op amp is necessary unless the signal source is very low imped-
ance to begin with. DC leakage currents at the ADuC812’s analog
inputs can cause measurable dc errors with external source imped-
ances of as little as 100
Ω. To ensure accurate ADC operation,
keep the total source impedance at each analog input less than
61
Ω. The table below illustrates examples of how source
impedance can affect dc accuracy.
Source
Error from 1
A
Error from 10
A
Impedance
Leakage Current
61
Ω
61 μV = 0.1 LSB
610 μV = 1 LSB
610
Ω
610 μV = 1 LSB
61 mV = 10 LSB
Although Figure 8 shows the op amp operating at a gain of 1,
you can configure it for any gain needed. Also, you can use an
instrumentation amplifier in its place to condition differential
signals. Use any modern amplifier that is capable of delivering
the signal (0 to VREF) with minimal saturation. Some single-supply,
rail-to-rail op amps that are useful for this purpose include, but
are not limited to, the ones given in Table VI. Check Analog
Devices literature (CD ROM data book, and so on) for details
about these and other op amps and instrumentation amps.
Table VI. Some Single-Supply Op Amps
Op Amp Model
Characteristics
OP181/OP281/OP481
Micropower
OP191/OP291/OP491
I/O Good up to VDD, Low Cost
OP196/OP296/OP496
I/O to VDD, Micropower, Low Cost
OP183/OP283
High Gain-Bandwidth Product
OP162/OP262/OP462
High GBP, Micro Package
AD820/AD822/AD824
FET Input, Low Cost
AD823
FET Input, High GBP
Keep in mind that the ADC’s transfer function is 0 V to VREF,
and any signal range lost to amplifier saturation near ground will
impact dynamic range. Though the op amps in Table VI are
capable of delivering output signals very closely approaching
ground, no amplifier can deliver signals all the way to ground when
powered by a single supply. Therefore, if a negative supply is
available, consider using it to power the front end amplifiers.
F
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