參數(shù)資料
型號(hào)： FMS7401LEN14
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Digital Power Controller
中文描述： 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14
封裝： PLASTIC, DIP-14
文件頁(yè)數(shù)： 32/80頁(yè)
文件大?。?/td> 1535K
代理商： FMS7401LEN14
FMS7401/7401L
PRODUCT SPECIFICATION
32
REV. 1.0.2 6/23/04
6
PWM Timer 1 Circuit
The Pulse Width Modulation (PWM) Timer 1 circuit, a programmable 12-bit PWM timer with a 3-bit prescaler can be config-
ured to operate in both PWM and Input Capture Modes. In PWM Mode, the Timer 1 circuit may be configured to generate
pulses of a specified duty cycle and period on the T1HS1 (G0), T1HS2 (G5), and/or ADSTROBE (G1) timer output ports. On
the other hand, in Input Capture Mode, the Timer 1 circuit may be configured to capture and store the current timer value at the
time of a trigger defined by the rising or falling edge of the T1HS2 (G5) input port. In addition, the T1HS1 and ADSTROBE
PWM outputs may be generated as in the PWM Mode.
The Timer 1 circuit backbone is a 12-bit programmable up-counter (TMR1) that is accessible by software, with read-only
access, through the 4-bit TMR1HI and 8-bit TMR1LO memory mapped registers where TMR1={TMR1HI, TMR1LO}.
1
Upon
a system reset or once entering a new Timer 1 mode of operation, the 12-bit TMR1 counter is initialized to 0x000. Once a
selected Timer 1 mode is enabled, the TMR1 counter will begin incrementing by the F
T1CLK
clock with the programmed divide
factor defined by a 3-bit prescaler. Once the TMR1 overflows, TMR1 is reinitialized to 0x000 and resumes incrementing until
software disables the mode. In PWM Mode, the TMR1 overflow value may be programmed by software where, in Input
Capture Mode, the TMR1 will overflow once the 0xFFF count completes. The Timer 1 circuit may be programmed to generate
microcontroller hardware interrupts with every TMR1 overflow and capture.
The Timer 1 F
T1CLK
clock may be programmed to operate from high to low frequencies with the use of the programmable
digital clock multiplier (PLL) and internal oscillator in order to provide the maximum flexibility for various PWM applica-
tions.
6.1
Software must access the six memory mapped PWM Timer 1 registers to configure and control the Timer 1 circuit.
1
The 8-bit
Prescale (PSCALE) register is used to configure the entire FMS7401/7401L clock structure including the Timer 1’s F
T1CLK
.
The 12-bit Timer 1 Compare A (T1CMPA), Timer 1 Compare B (T1CMPB), and Timer 1 Reload (T1RA) registers are used to
define the PWM output signal’s duty cycle and period. The 5-bit Dead Time (DTIME) register is used to define the time delay
(T
DT
) between the PWM T1HS1 and T1HS2 edge transitions while in PWM Mode. The Timer 1 Control (T1CNTRL) register
is used to select Timer 1’s operating mode, enable its PWM output signals, and control its hardware interrupt (TMRI1).
PWM Timer 1 Configuration Registers
6.1.1 PSCALE Register and Timer 1 Clock Configuration
Although the PSCALE register is part of the PWM Timer 1 circuit, its register bits configure the clock structure for the entire
FMS7401/7401L along with the Timer 1 clock (F
T1CLK
). Refer to the
Clock Circuit
section of the datasheet for details regard-
ing the device’s clock structure. The F
T1CLK
source may be supplied by either the programmable F
PWMCLK
PLL output or the
main instruction (F
ICLK
) clock. Once the F
T1CLK
source is selected, it may not be changed while the Timer 1 circuit is in PWM
mode and running or in Input Capture Mode (run mode). Upon a system reset, the PSCALE register is automatically initialized
to 0x00.
Bit 7 of the PSCALE register is the PLL circuit enable (PLLEN) bit. Before using any of the PLL outputs, software must
enable the PLL circuit and wait the T
PLL_LOCK
to ensure that the PLL is locked into its appropriate frequency and in phase. The
PLLEN bit may not be changed while the Timer 1 circuit is in run mode. Any attempts to write to PLLEN under this condition
will be ignored and its value will remain unchanged.
Bits 6 and 5 (FS[1:0]) of the PSCALE register are the bits used to select between the different output frequencies available to
the PLL’s F
PWMCLK
output signal. FS selects between the four available PLL divide factors (divide-by-1/2/4/8) selecting an out-
put frequency of 8/16/32/64MHz (see
Table 13
). The FS bits may be changed by software at any time; however, if the Timer 1
circuit is in run mode, the FS value will not change the F
PWMCLK
output frequency until after the TMR1 counter overflows end-
ing the current PWM cycle. The last FS value at the TMR1 counter overflow will dictate the divide factor of the F
PWMCLK
out-
put for the next PWM cycle. When reading FS, the value reported will be the last value written by software and may not
necessarily reflect the divide factor for the current PWM cycle.
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