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參數(shù)資料
| 型號： | FMS7401LEN14 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Digital Power Controller |
| 中文描述： | 8-BIT, EEPROM, 2.04 MHz, MICROCONTROLLER, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 8/80頁 |
| 文件大?。?/td> | 1535K |
| 代理商： | FMS7401LEN14 |
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FMS7401/7401L
PRODUCT SPECIFICATION
8
REV. 1.0.2 6/23/04
1
Reset Circuit
The reset circuit in the FMS7401/7401L contains four input conditions that trigger a main system reset. When the main system
reset is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization registers) and
I/Os to their initial states (see
Table 1
). During the system reset sequence, the instruction core execution is halted allowing time
for the internal oscillator and other analog circuits to stabilize. Once the system reset sequence completes, the device will begin
with its normal operation executing the instruction program residing in the code EEPROM memory. The time required for the
system reset sequence to complete (T
RESET
) is dependent on the individual trigger condition and is defined in the
Electrical
Characteristics
section of the datasheet. The four reset trigger conditions are as follows:
Power-on Reset (POR)
External Reset
Brown-out Reset (BOR)
Watchdog Reset
1
2
Table 1. Default Register States
1.1
The Power-on Reset (POR) circuit maintains the device in a reset state until Vcc reaches a voltage level high enough to guaran-
tee proper device operation. The POR circuit is sensitive to the different Vcc ramp rates and must be within S
the
Electrical Characteristics
section of the datasheet.
FMS7401L Power-on Reset Circuit
Vcc
as specified in
The POR circuit does not generate a system reset when Vcc is falling. This feature is performed by the Brown-out Reset (BOR)
circuit and must be enabled by the BOREN bit of the Initialization Register 1.
before the next power-up sequence, it is necessary to enable the BOR circuit and/or reset the device externally through the
RESET pin.
4
In the case where Vcc does not drop to 0V
1
1.2
The device may be externally reset through the RESET input pin if the POR/BOR circuits cannot be used to properly reset the
device in the application. The RESET input pin contains an internal pull-up resistor making it an active low signal. Therefore,
to issue a device system reset the RESET input should be held low for at least 10μS before being released (i.e. returned to a
high state). While the RESET input is held low, the internal oscillator and other analog circuits are kept in a low power state
reducing the current consumption of the device (a state resembling Halt Mode). In addition, the I/O pins are all initialized to an
input tri-state configuration unless defaulted otherwise.
At the rising edge of the RESET input signal, the main system reset
sequence is triggered releasing the internal oscillator and other analog circuits so that they may be initialized and begin their
normal operation.
FMS7401L External Reset
1
5
1.3
The Brown-out Reset (BOR) circuit is one of the on-chip analog comparator peripherals and must be enabled through the
BOREN bit of the Initialization Registers 1.
The BOR circuit is used to hold the device in a reset state when Vcc drops below
a fixed threshold defined in the
Electrical Characteristics
section of the datasheet. While in reset, the device is held in its initial
condition until Vcc rises above the fixed/power-on threshold. Shortly after Vcc rises above the fixed/power-on threshold, the
internal system reset sequence is started. Once the system reset sequence completes, the device will begin with its normal
operation executing the instruction program residing in the code EEPROM memory.
FMS7401L Brown-out Reset Circuit
4
Peripheral/Register
External Reset
POR
G1, G2, G3, G4, G6, G7
High-impedance input (tri-state input)
G0, G5
Defined by Init Reg. 4 (see
Table 28
)
SRAM Memory
No change
Unspecified
Stack Pointer
0xF
0xF
Status Register
0x80
0x80
T1CMPA, T1CMPB and T1RA Registers
0xFFF
0xFFF
DTIME Register
0x1F
0x1F
All other memory mapped register not listed above.
3
0x00
0x00
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