- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375914 > FS6131-01 (Electronic Theatre Controls, Inc.) Programmable Line Lock Clock Generator IC PDF資料下載
參數(shù)資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數(shù)： | 30/39頁 |
| 文件大?。?/td> | 435K |
| 代理商： | FS6131-01 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
30
FS6131-01
Programmable Line Lock Clock Generator IC
11.0 Applications Information
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applica-
tions, such as an increase in clock jitter and a rise in
electromagnetic emissions from the board. Using a prop-
erly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflec-
tions.
11.1
If a PECL interface is desired, the transmission line must
be terminated using a Thévenin, or dual, termination. The
output stage can only sink current in the PECL mode,
and the amount of sink current is set by a programming
resistor on the LOCK/IPRG pin. Source current is pro-
vided by the pull-up resistor that is part of the Thévenin
termination.
PECL Output Mode
Figure 27: Thévenin Termination (PECL)
R
p1
IPRG
CLKN
CLKP
{
from
PLL
R
n1
R
p2
R
n2
R
i
LOAD
z
L
z
L
z
O
PECL Mode Output
V
CC
V
CC
Thévenin termination uses two resistors per transmission
line. The parallel resistance of the termination resistors
should be sized to equal the transmission line imped-
ance, taking into account the driver sink current, the de-
sired rise and fall times, and the V
IH
and V
IL
specifications
of the load.
11.1.1
In PECL mode, the output driver does not source current,
so the V
IH
value is determined by the ratios of the termi-
nating resistors using the equation
Example Calculation
2
1
1
R
p
p
p
CC
NMH
R
R
V
V
+
×
=
where R
p1
is the pull-up resistor, R
p2
is the pull-down re-
sistor, and V
NMH
is the desired noise margin, and
V
V
=
The resistor ratio must also match the line impedance via
the equation
R
z
=
NMH
CC
IH
V
.
2
1
2
1
+
p
p
p
p
L
R
R
R
where z
L
is the line impedance.
Combining these equations, and solving for R
p1
gives
+
=
NMH
CC
NMH
V
L
L
p
V
V
z
z
R
1
If the load’s V
IH(min)
= V
CC
– 0.6, choose a V
NMH
= 0.45V. If
the line impedance is 75
, then R
p1
is about 82
. Sub-
stituting into the equation for line impedance and solving
for R
p2
gives a value of 880
(choose 910
).
To solve for the load’s V
IL
, an output sink current must be
programmed via the IPRG pin. If the desired V
IH
= V
CC
–
1.6, choose V
CC
– 2.0 for some extra margin. A sink cur-
rent of 25mA through the 82
resistor generates a 2.05V
drop. The sink current is programmed via the IPRG pin,
where the ratio of IPRG current to output sink current is
1:4. An IPRG programming resistor of 750
at V
DD
= 5V
generates 6.6mA, or about 27mA output sink current.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FS6282 | DUAL PLL CLOCK GENERATOR IC |
| FS6282-03 | DUAL PLL CLOCK GENERATOR IC |
| FS6M07652RTC | Time-Delay Relay; Contacts:SPST-NO; Time Range:0.2 sec. to 20 sec.; Timing Function:Delay-On-Make; Voltage Rating:120V |
| FS6M07652RTCTU | Fairchild Power Switch(FPS) |
| FS6M07652RTCYDT | Fairchild Power Switch(FPS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。