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參數資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數： | 31/39頁 |
| 文件大小： | 435K |
| 代理商： | FS6131-01 |
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31
FS6131-01
Programmable Line Lock Clock Generator IC
11.2
If a CMOS interface is desired, a transmission line is typi-
cally terminated using a series termination. Series termi-
nation adds no dc loading to the driver, and requires less
power than other resistive termination methods. In addi-
tion, no extra impedance exists from the signal line to a
reference voltage, such as ground.
CMOS Output Mode
Figure 28: Series Termination (CMOS)
R
S
z
L
z
O
DRIVER
RECEIVE
LINE
As shown in Figure 28, the sum of the driver’s output im-
pedance (z
O
) and the series termination resistance (R
S
)
must equal the line impedance (z
L
). That is,
z
R
=
O
L
S
z
.
When the source impedance (z
O
+R
S
) is matched to the
line impedance, then by voltage division the incident
wave amplitude is one-half of the full signal amplitude.
(
R
z
O
+
However, the full signal amplitude may take up to twice
as long as the propagation delay of the line to develop,
reducing noise immunity during the half-amplitude period.
Note that the voltage at the receive end must add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal may be reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also, note that the output driver
impedance will vary slightly with the output logic state
(high or low).
2
)
(
)
V
z
R
z
V
V
L
S
S
+
O
i
=
+
=
11.3
Connection of devices to a standard-mode implementa-
tion of the I
2
C-bus is similar to that shown in Figure 29.
Selection of the pull-up resistors (R
P
) and the optional
series resistors (R
S
) on the SDA and SCL lines depends
on the supply voltage, the bus capacitance, and the
number of connected devices with their associated input
currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines.
A guideline is
Serial Communications
bus
r
P
C
t
R
×
<
2
,
where t
r
is the maximum rise time (minus some margin)
and C
bus
is the total bus capacitance. Assuming an I
2
C
controller and 8 to 10 other devices on the bus, including
this one, results in values in the 5k
to 7k
range. Use of
a series resistor to provide protection against high volt-
age spikes on the bus will alter the values for R
P
.
Figure 29: Connections to the Serial Bus
R
P
SDA
SCL
Data In
Data Out
Clock Out
TRANSMITTER
Data In
Data Out
RECEIVER
Clock In
R
P
R
S
(optional)
R
S
(optional)
R
S
(optional)
R
S
(optional)
11.3.1
More information on the I
2
C-bus can be found in the
document The I
2
C-bus And How To Use It (Including
Specifications), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com
.
For More Information
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相關代理商/技術參數 |
參數描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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