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參數(shù)資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數(shù)： | 33/39頁 |
| 文件大?。?/td> | 435K |
| 代理商： | FS6131-01 |
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33
FS6131-01
Programmable Line Lock Clock Generator IC
Next, express the output and input frequencies as a ratio
of f
CLK
to f
REF
, where f
CLK
has also been converted to a
product of prime numbers.
00
.
100000000
CLK
f
(
)
×
×
×
×
=
=
11
7
5
3
2
5
2
81
.
14318181
1
7
2
5
8
8
REF
f
Simplifying the above equation yields
f
(
)
(
)
7
3
11
5
2
2
1
3
×
×
×
=
REF
CLK
f
.
(Eqn. 2)
Deciding how to apportion the denominator integers be-
tween the Reference Divider and the Post Divider is an
iterative process. To obtain the best performance, the
VCO should be operated at the highest frequency possi-
ble without exceeding its upper limit of 230MHz. (see
Table 16). The VCO frequency (f
VCO
) can be calculated
by
R
F
REF
VCO
N
N
f
f
×
=
.
Recall that the Reference Divider can have a value be-
tween 1 and 4096, but the Post Divider is limited to val-
ues derived from
N
N
×
=
where the values N
P1
, N
P2
, and N
P3
are found in Table 8.
In this example, the smallest integer that can be removed
from the denominator of Eqn. 2 is three. Set the Post Di-
vider at N
Px
=3, and the ratio of f
CLK
to f
REF
becomes (from
Eqn. 1)
(
(
3
REF
f
Unfortunately, a Post Divider modulus of three requires a
VCO frequency of 300MHz, which is greater than the al-
lowable f
VCO
noted in Table 16. For the best PLL per-
formance, program the Post Divider modulus to allow the
VCO to operate at a nominal frequency that is at least
70MHz but less then 230MHz. Therefore, the Reference
Divider cannot be reduced below the modulus of 3
2
×
7 (or
63) as shown in Eqn. 2.
However, the VCO can still be operated at a frequency
higher than f
CLK
. Multiplying both the numerator and the
denominator by two does not alter the output frequency,
but it does increase the VCO frequency.
(
(
Px
R
REF
N
N
f
(Eqn. 3)
3
2
1
P
P
P
Px
N
N
×
)
)
3
1
7
11
5
×
2
1
3
×
×
×
=
CLK
f
.
)
)
2
1
63
880
2
1
7
3
2
11
5
2
1
2
1
3
×
=
×
×
×
×
×
=
×
=
F
CLK
N
f
As Eqn. 3 shows, the VCO frequency can be doubled by
multiplying the Feedback Divider by two. Set the Post
Divider to two to return the output frequency to the de-
sired modulus. These divider settings place the VCO fre-
quency at 200MHz.
12.2
To generate 100.000MHz from 14.318MHz, program the
following (refer to Figure 30):
Set the Reference Divider input to select the VCXO
via REFDSRC=0
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF=0 and
PDFBK=0
Set the Reference Divider (N
R
) to a modulus of 63 via
REFDIV[11:0]
Set the Feedback Divider input to select the VCO via
FBKDSRC=1
Set the Feedback Divider (N
F
) to a modulus of 880
via FBKDIV[14:0]
Set N
P1
=2, N
P2
=1, and N
P3
=1 for a combined Post
Divider modulus of N
Px
=2 via POST1[1:0],
POST2[1:0], and POST3[1:0].
Select the internal loop filter via EXTLF=0
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
Set VCOSPD=0 to select the VCO high speed range
Example Programming
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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