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參數(shù)資料
| 型號： | FS6131-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Programmable Line Lock Clock Generator IC |
| 中文描述： | 可編程線鎖定時鐘發(fā)生器IC |
| 文件頁數(shù)： | 39/39頁 |
| 文件大?。?/td> | 435K |
| 代理商： | FS6131-01 |
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39
FS6131-01
Programmable Line Lock Clock Generator IC
The goal is to choose the highest crystal frequency from
Table 10 that generates the smallest value of N
R.
The equation establishing the output frequency (f
CLK
) as a
function of the input VCXO frequency is
N
f
R
F
VCXO
CLK
N
f
=
(Eqn. 1)
where N
F
is the Feedback Divider modulus.
Choose a few different crystal frequencies from Table 10
and factor both the input VCXO and output clock fre-
quencies into prime numbers. Look for the factors that
will give the smallest modulus for N
R
with the largest
F
VCXO
. The output and VCXO frequencies and the re-
duced factors from Eqn. 1 are in Table 25.
Table 25: Clock Regenerator Example
VCXO FREQUENCY
FROM Table 10
(f
VCXO
, MHz)
VCXO
CLK
f
f
R
F
N
N
20.00
20000000
51840000
51840000
125
8
324
19.44
19440000
51840000
3
25.248
25248000
51840000
263
135
540
24.576
24576000
64
A 19.44MHz crystal provides the smallest modulus for N
R
(N
R
=3) with the highest crystal frequency.
Finally, choose a Post Divider (N
Px
) modulus that keeps
the VCO frequency in its most comfortable range. The
VCO frequency (f
VCO
) can be calculated by
f
f
=
Selecting an overall modulus of N
Px
=3 sets the VCO fre-
quency at 155.52MHz when the loop is locked.
Px
CLK
VCO
N
15.2
To generate a de-jittered output frequency of 51.84MHz
from an 8kHz reference, program the following (refer to
Figure 33):
Program the VCXO Control ROM to 3 via
XLROM[2:0] to select an external 19.44MHz crystal
Enable the VCXO fine tune via XLVTEN=1
Enable the Crystal Loop PFD via XLPDEN=0 and
XLSWAP=0
Set the Reference Divider input to select the VCXO
via REFDSRC
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF and PDFBK
Set the Reference Divider (N
R
) to a modulus of 3 via
REFDIV[11:0]
Set the Feedback Divider input to select the VCO via
FBKDSRC
Set the Feedback Divider (N
F
) to a modulus of 8 via
FBKDIV[14:0]
Set N
P1
=1, N
P2
=3, and N
P3
=1 for a combined Post
Divider modulus of N
Px
=3 via POST1[1:0],
POST2[1:0], and POST3[1:0].
Select the internal loop filter via EXTLF
Set VCOSPD=0 to select the VCO high speed range
These settings provide the highest frequency at the Main
Loop Phase Frequency Detector of 6.48MHz. The use of
a 19.44MHz crystal requires that XLROM[2:0] be set to
three as shown in Table 10.
Example Programming
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FS6131-01G | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Programmable Line Lock Clock Generator IC |
| FS6131-01G-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01G-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTD | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK (IND) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| FS6131-01I-XTP | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C PROG PLL CLK IND RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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