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參數(shù)資料
| 型號： | FS6232-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TWO WAY MP MOTHERBOARD CLOCK GENERATOR IC |
| 中文描述： | 雙向手機主板時鐘發(fā)生器芯片 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 194K |
| 代理商： | FS6232-01 |
AMERICAN MICROSYSTEMS, INC.
September 2000
Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent
No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice.
ISO9001
9.18.00
IntSKS
FS6232
-01
Two-Way MP Motherboard Clock Generator IC
1.0 Features
Generates all clocks required for single and two-way
multi-processor (MP) platforms, including:
Four differential current-mode Host clock pairs
Four 66.67MHz 3.3V CK66 clock outputs
Ten 33.3MHz 3.3V PCI clock outputs
Two 3.3V Memory Reference clock outputs
Two 48MHz 3.3V CK48 clock outputs
Two buffered copies of the crystal reference
Control of current-mode Host clocks via IREF current
programming pin and ISEL_0:1 current multiplier pins
Host clock frequency selection via the SEL_A,
SEL_B, and SEL133/100# pins
Active-low PWR_DWN# signal allows one complete
clock cycle on each clock outputs and then shuts
down the crystal oscillator, PLLs, and outputs
Spread-spectrum modulation (-0.5% at 31.5kHz) of
SSCG PLL clocks, enabled via SS_EN# input
Supports test mode and tristate output control to fa-
cilitate board testing
Available in a 56-pin SSOP and TSSOP
Table 1: Clock Parameters
CLOCK
GROUP
#
PINS
SUPPLY
VOLTAGE
SUPPLY
GROUP
FREQ.
(MHz)
PHASE
SKEW
(MAX)
HOST_P
4
0°
HOST_N
4
3.3V
VDD_H
133.33
100.00
180°
150ps
Pair to
Pair
MREF_P
MREF_N
CK66
PCI
CK48
REF
1
1
4
0°
3.3V
VDD_M
66.67
50.00
180°
0°
0°
0°
0°
-
3.3V
3.3V
3.3V
3.3V
VDD_66
VDD_P
VDD_48
VDD_R
66.67
33.33
48.008
14.318
250ps
300ps
-
-
10
2
2
Table 2: Clock Offsets
RELATION
PHASE
MIN
TYP
MAX
CK66 leads PCI
0°
1.5ns
3.5ns
Figure 1: Block Diagram
Crystal
Oscillator
XOUT
XIN
PWR_DWN#
FS6232
CK66_0:3
VSS_66
adjust
IREF
REF_0:1
VSS_R
VDD_R
ISEL_0:1
÷3
÷4
÷4
VSS_M
VDD_M
MREF_P
MREF_N
VDD_66
÷1
÷2
VSS_H
VDD_H
HOST_P1:4
HOST_N1:4
SEL133/100#
SEL_A:B
PCI_0:9
VSS_P
÷2
VDD_P
CK48_0:1
VSS_48
VDD_48
delay
PLL
SSCG
PLL
Control
SS_EN#
Figure 2: Pin Configuration
1
48
2
3
4
5
6
7
8
47
46
45
44
43
42
41
REF_0 / ISEL_0
VDD_R
VSS_R
XOUT
VSS_P
9
10
11
12
13
14
15
16
CK66_3
VSS_66
SEL133/100#
VSS
17
18
19
20
21
22
23
MREF_P
MREF_N
40
39
38
37
36
35
34
33
SS_EN#
HOST_N1
VSS_H
HOST_P2
32
31
30
29
IREF
24
F
VDD
HOST_P1
28
27
26
25
XIN
VSS_M
HOST_N2
VDD_66
PWR_DWN#
VDD_H
HOST_N4
HOST_P4
HOST_N3
HOST_P3
VDD_H
VDD_P
P
P
P
P
49
50
52
51
53
54
56
55
REF_1 / ISEL_1
PCI_0
PCI_1
PCI_2
PCI_3
VSS_P
VDD_P
PCI_4
PCI_5
PCI_6
PCI_7
VSS_P
VDD_P
PCI_8
PCI_9
VDD_48
CK48_0 / SEL_A
CK48_1 / SEL_B
VSS_48
CK66_2
CK66_1
CK66_0
VDD_66
VSS_66
VSS_H
VDD_M
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