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參數(shù)資料
| 型號： | FS6232-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TWO WAY MP MOTHERBOARD CLOCK GENERATOR IC |
| 中文描述： | 雙向手機(jī)主板時鐘發(fā)生器芯片 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 194K |
| 代理商： | FS6232-01 |
AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
10
FS6232-01
Two-Way MP Motherboard Clock Generator IC
ISO9001
Table 15: AC Timing Specifications, continued
Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T
A
= 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and
are not currently production tested to any specific limits. MIN and MAX characterization data are
±
3
σ
from typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
PCI_0:9 Clock Outputs
Duty Cycle *
d
t
Ratio of high pulse width to one clock period,
measured at 1.5V
One clock output relative to another at 1.5V
From rising edge to rising edge at 1.5V, C
L
= 30pF
Measured at 0.4V – 2.4V; C
L
= 10pF
Measured at 0.4V – 2.4V; C
L
= 30pF
Measured at 2.4V – 0.4V; C
L
= 10pF
Measured at 2.4V – 0.4V; C
L
= 30pF
45
55
%
Clock Skew *
Jitter, Period (peak-peak) *
t
sk(o)
t
j(
P)
t
r min
t
r max
t
f min
t
f max
500
500
ps
ps
0.5
Rise Time *
2.0
ns
0.5
Fall Time *
2.0
ns
CK66_0:3 Clock Outputs
Duty Cycle *
d
t
Ratio of high pulse width to one clock period,
measured at 1.5V
One clock output relative to another at 1.5V
From rising edge to rising edge at 1.5V, C
L
= 30pF
Measured at 0.4V – 2.4V; C
L
= 10pF
Measured at 0.4V – 2.4V; C
L
= 30pF
Measured at 2.4V – 0.4V; C
L
= 10pF
Measured at 2.4V – 0.4V; C
L
= 30pF
45
55
%
Clock Skew *
Jitter, Period (peak-peak) *
t
sk(o)
t
j(
P)
t
r min
t
r max
t
f min
t
f max
250
300
ps
ps
0.5
Rise Time *
2.0
ns
0.5
Fall Time *
2.0
ns
REF_0:1 Clock Outputs
Duty Cycle *
d
t
Ratio of high pulse width to one clock period,
measured at 1.5V
From rising edge to rising edge at 1.5V, C
L
= 20pF
Measured at 0.4V – 2.4V; C
L
= 10pF
Measured at 0.4V – 2.4V; C
L
= 20pF
Measured at 2.4V – 0.4V; C
L
= 10pF
Measured at 2.4V – 0.4V; C
L
= 20pF
45
55
%
Jitter, Period (peak-peak) *
t
j(
P)
t
r min
t
r max
t
f min
t
f max
1000
ps
1.0
Rise Time *
4.0
ns
1.0
Fall Time *
4.0
ns
CK48_0:1 Clock Outputs
Duty Cycle *
d
t
Ratio of high pulse width to one clock period,
measured at 1.5V
From rising edge to rising edge at 1.5V, C
L
= 20pF
Measured at 0.4V – 2.4V; C
L
= 10pF
Measured at 0.4V – 2.4V; C
L
= 20pF
Measured at 2.4V – 0.4V; C
L
= 10pF
Measured at 2.4V – 0.4V; C
L
= 20pF
45
55
%
Jitter, Period (peak-peak) *
t
j(
P)
t
r min
t
r max
t
f min
t
f max
350
ps
1.0
Rise Time *
4.0
ns
1.0
Fall Time *
4.0
ns
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