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參數(shù)資料
| 型號(hào)： | FS6232-01 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | TWO WAY MP MOTHERBOARD CLOCK GENERATOR IC |
| 中文描述： | 雙向手機(jī)主板時(shí)鐘發(fā)生器芯片 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | FS6232-01 |
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AMERICAN MICROSYSTEMS, INC.
September 2000
9.18.00
2
FS6232-01
Two-Way MP Motherboard Clock Generator IC
ISO9001
Table 3: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI
U
= Input with Internal Pull-Up; DI
D
= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active-low pin
PIN
TYPE
NAME
DESCRIPTION
SUPPLY
CK48_0
SEL_A
CK48_1
SEL_B
CK66_0:3
HOST_P1
HOST_N1
HOST_P2
HOST_N2
HOST_P3
HOST_N3
HOST_P4
HOST_N4
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL
One of two latched inputs that select the HOST and MREF output frequency
Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL
Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The
current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1
25
DIO
VDD_48
26
DIO
VDD_48
35, 34, 31, 30
DO
VDD_66
50, 51
AO
VDD_H
47, 48
AO
Host clock pair #2; one of six pairs of current-steering differential current-mode outputs
VDD_H
44, 45
AO
Host clock pair #3; one of six pairs of current-steering differential current-mode outputs
VDD_H
41, 42
AO
Host clock pair #4; one of six pairs of current-steering differential current-mode outputs
VDD_H
39
AI
IREF
A fixed precision resistor from this pin to ground provides a reference current used for the dif-
ferential current-mode HOST clock outputs
One clock (180° out of phase with MREF_P) in a pair of outputs provided as a reference clock
to a memory clock driver
One clock in a pair of outputs provided as a reference clock to a memory clock driver
VDD
54
DO
MREF_N
VDD_M
55
DO
MREF_P
VDD_M
8, 9, 11, 12,
14, 15, 17, 18,
20, 21
DO
PCI_0:9
Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns
VDD_P
28
DI
PWR_DWN#
Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all
clocks in low state. Complete clock cycles on all outputs will occur before shut down begins.
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
One of two 3.3V buffered copies of the crystal reference frequency clock
One of two latched inputs that select the multiplying factor of the IREF reference current for the
HOST pair outputs
Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency
VDD_48
REF_0
2
DIO
ISEL_0
VDD_R
REF_1
3
DIO
ISEL_1
VDD_R
23
DI
SEL133/100#
VDD_48
52
DI
SS_EN#
Active low spread-spectrum enable turns on spread spectrum modulation
VDD_M
38
27
P
P
P
P
P
P
P
P
P
P
P
P
P
P
AI
AO
VDD
VDD_48
VDD_66
VDD_H
VDD_M
VDD_P
VDD_R
VSS
VSS_48
VSS_66
VSS_H
VSS_M
VSS_P
VSS_R
XIN
XOUT
3.3V core power supply
3.3V power supply for CK48 clock outputs
3.3V power supply for CK66 clock outputs
3.3V power supply for the differential HOST clock outputs
3.3V power supply for MREF clock outputs
3.3V power supply for PCI clock outputs
3.3V power supply for the REF clock output and the crystal oscillator
Core ground
Ground for the CK48 clock outputs
Ground for the CK66 clock outputs
Ground for the differential HOST clock outputs
Ground for the MREF clock outputs
Ground for the PCI clock outputs
Ground for the REF clock outputs and the crystal oscillator
14.318MHz crystal oscillator input
14.318MHz crystal oscillator output
-
-
-
-
-
-
-
-
-
29, 36
43, 49
56
10, 16, 22
4
37
24
32, 33
40, 46
53
7, 13, 19
1
5
6
-
-
-
-
VDD_R
VDD_R
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