參數(shù)資料
型號(hào)： FW32305
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁數(shù)： 104/152頁
文件大?。?/td> 1625K
代理商： FW32305
104
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Internal Registers
(continued)
Table 91. PHY Core Layer Control Register Description
Bit
31
Field Name
rdDone
Type
RU
Description
This bit is cleared to 0 by the FW323 when either bit 15 (rdReg) or bit 14 (wrReg)
is set. This bit is set when a register transfer is received from the PHY core.
Reserved.
Bits 30:28 return 0s when read.
This is the address of the register most recently received from the PHY core.
This field is the contents of a PHY core register which has been read.
RWU This bit is set by software to initiate a read request to a PHY core register and is
cleared by hardware when the request has been sent. Bit 14 (wrReg) and bit 15
(rdReg) must be used exclusively.
RWU This bit is set by software to initiate a write request to a PHY core register and is
cleared by hardware when the request has been sent. Bit 14 (wrReg) and bit 15
(rdReg) must be used exclusively.
R
Reserved.
Bits 13:12 return 0s when read.
RW
This field is the address of the PHY core register to be written or read.
RW
This field is the data to be written to a PHY core register and is ignored for reads.
30:28
27:24
23:16
15
Reserved
rdAddr
rdData
rdReg
R
RU
RU
14
wrReg
13:12
11:8
7:0
Reserved
regAddr
wrData
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FW32306 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW323061394 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW323061394A 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW-33-01-G-D-200-065 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk
FW-33-01-L-D-200-075 制造商:Samtec Inc 功能描述:.050'' BOARD SPACERS - Bulk
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