- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370260 > FW32305 1394A PCI PHY/Link Open Host Controller Interface PDF資料下載
參數(shù)資料
| 型號： | FW32305 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口 |
| 文件頁數(shù)： | 128/152頁 |
| 文件大?。?/td> | 1625K |
| 代理商： | FW32305 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁當(dāng)前第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁
128
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Internal Registers
(continued)
Table 111. Isochronous Receive Context Control Register Description
Bit
31
Field Name
bufferFill
Type
RSC
Description
When this bit is set, received packets are placed back-to-back to com-
pletely fill each receive buffer. When this bit is cleared, each received
packet is placed in a single buffer. If bit 28 (multiChanMode) is set to 1,
then this bit must also be set to 1. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set.
When this bit is 1, received isochronous packets include the complete
4-byte isochronous packet header seen by the link layer. The end of the
packet is marked with an xferStatus in the first doublet, and a 16-bit
timeStamp indicating the time of the most recently received (or sent)
cycleStart packet. When this bit is cleared, the packet header is stripped
off of received isochronous packets. The packet header, if received,
immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set.
When this bit is set, the context begins running only when the 13-bit
cycleMatch field (bits 24:12) in the isochronous receive context match
register matches the 13-bit cycleCount field in the cycleStart packet. The
effects of this bit, however, are impacted by the values of other bits in
this register. Once the context has become active, hardware clears this
bit. The value of this bit must not be changed while bit 10 (active) or bit
15 (run) is set.
When this bit is set, the corresponding isochronous receive DMA context
receives packets for all isochronous channels enabled in the isochro-
nous receive channel mask high and isochronous receive channel mask
low registers. The isochronous channel number specified in the isochro-
nous receive DMA context match register is ignored. When this bit is
cleared, the isochronous receive DMA context receives packets for the
channel number specified in the context match register. Only one isoch-
ronous receive DMA context may use the isochronous receive channel
mask registers. If more that one isochronous receive context control reg-
ister has this bit set, then results are undefined. The value of this bit
must not be changed while bit 10 (active) or bit 15 (run) is set to 1.
Reserved.
Bits 27:16 return 0s when read.
This bit is set by software to enable descriptor processing for the context
and cleared by software to stop descriptor processing. The FW323
changes this bit only on a hardware or software reset.
Reserved.
Bits 14:13 return 0s when read.
Software sets this bit to cause the FW323 to continue or resume descrip-
tor processing. The FW323 clears this bit on every descriptor fetch.
The FW323 sets this bit when it encounters a fatal error and clears the
bit when software resets bit 15 (run).
The FW323 sets this bit to 1 when it is processing descriptors.
Reserved.
Bits 9:8 return 0s when read.
This field indicates the speed at which the packet was received.
30
isochHeader
RSC
29
cycleMatchEnable
RSCU
28
multiChanMode
RSC
27:16
15
Reserved
run
R
RSCU
14:13
12
Reserved
wake
R
RSU
11
dead
RU
10
9:8
7:5
active
Reserved
spd
RU
R
RU
000 = 100 Mbits/s.
001 = 200 Mbits/s.
010 = 400 Mbits/s. All other values are reserved.
Following an INPUT_* command, the error or status code is indicated in
this field.
4:0
event code
RU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW352 | |
| FW501 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO |
| FW801A | Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801A-DB | Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801 | One-Cable Transceiver/Arbiter Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW32306 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394A | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW-33-01-G-D-200-065 | 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk |
| FW-33-01-L-D-200-075 | 制造商:Samtec Inc 功能描述:.050'' BOARD SPACERS - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。