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參數(shù)資料
| 型號(hào)： | FW32305 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開(kāi)放主機(jī)控制器接口 |
| 文件頁(yè)數(shù)： | 3/152頁(yè) |
| 文件大小： | 1625K |
| 代理商： | FW32305 |
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Agere Systems Inc.
3
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Table of Contents
(continued)
Contents
Page
Isochronous Receive Channel Mask Low Register ..........................................................................................84
Interrupt Event Register ...................................................................................................................................86
Interrupt Mask Register ....................................................................................................................................89
Isochronous Transmit Interrupt Event Register ................................................................................................91
Isochronous Transmit Interrupt Mask Register ................................................................................................93
Isochronous Receive Interrupt Event Register .................................................................................................94
Isochronous Receive Interrupt Mask Register .................................................................................................96
Fairness Control Register ................................................................................................................................97
Link Control Register ........................................................................................................................................99
Node Identification Register ...........................................................................................................................101
PHY Core Layer Control Register ..................................................................................................................103
Isochronous Cycle Timer Register .................................................................................................................105
Asynchronous Request Filter High Register ..................................................................................................107
Asynchronous Request Filter Low Register ...................................................................................................110
Physical Request Filter High Register ............................................................................................................113
Physical Request Filter Low Register ............................................................................................................116
Asynchronous Context Control Register ........................................................................................................119
Asynchronous Context Command Pointer Register .......................................................................................121
Isochronous Transmit Context Control Register ............................................................................................123
Isochronous Transmit Context Command Pointer Register ...........................................................................125
Isochronous Receive Context Control Register .............................................................................................127
Isochronous Receive Context Command Pointer Register ............................................................................129
Isochronous Receive Context Match Register ...............................................................................................131
FW323 Vendor Specific Registers .................................................................................................................133
Isochronous DMA Control ..............................................................................................................................134
Asynchronous DMA Control ...........................................................................................................................135
Link Options ...................................................................................................................................................136
Crystal Selection Considerations ..........................................................................................................................138
Load Capacitance ..........................................................................................................................................138
Board Layout ..................................................................................................................................................138
Absolute Maximum Ratings ..................................................................................................................................138
Electrical Characteristics ......................................................................................................................................139
Timing Characteristics ..........................................................................................................................................141
ac Characteristics of Serial EEPROM Interface Signals ......................................................................................141
Internal Register Configuration .............................................................................................................................144
PHY Core Register Map for Cable Environment ............................................................................................144
PHY Core Register Fields for Cable Environment .........................................................................................145
Outline Diagrams ..................................................................................................................................................150
128-Pin TQFP ................................................................................................................................................150
Figure
Page
Figure 1. FW323 Functional Block Diagram .............................................................................................................7
Figure 2. PHY Core Block Diagram ........................................................................................................................12
Figure 3. Pin Assignments for FW323 ....................................................................................................................13
Figure 4. Application Schematic for FW323 ...........................................................................................................19
Figure 5. Bus Timing ............................................................................................................................................142
Figure 6. Write Cycle Timing ................................................................................................................................142
Figure 7. Data Validity ..........................................................................................................................................142
Figure 8. Start and Stop Definition .......................................................................................................................143
Figure 9. Output Acknowledge .............................................................................................................................143
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相關(guān)代理商/技術(shù)參數(shù) |
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| FW32306 | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
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| FW323061394A | 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW-33-01-G-D-200-065 | 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk |
| FW-33-01-L-D-200-075 | 制造商:Samtec Inc 功能描述:.050'' BOARD SPACERS - Bulk |
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