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參數(shù)資料
| 型號： | FW32305 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機控制器接口 |
| 文件頁數(shù)： | 88/152頁 |
| 文件大?。?/td> | 1625K |
| 代理商： | FW32305 |
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88
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Internal Registers
(continued)
Table 75. Interrupt Event Register Description
(continued)
Bit
15:10
9
Field Name
Reserved
lockRespErr
Type
RU
RU
Description
Reserved.
Bits 15:10 return 0s when read.
Indicates that the FW323 sent a lock response for a lock request to
a serial bus register, but did not receive an ack_complete.
Indicates that a host bus error occurred while the FW323 was
trying to write a 1394 write request, which had already been given
an ack_complete, into system memory.
Isochronous Receive DMA Interrupt.
Indicates that one or more
isochronous receive contexts have generated an interrupt. This is
not a latched event; it is the ORing of all bits in the isochronous
receive interrupt event and isochronous receive interrupt mask
registers. The isochronous receive interrupt event register indi-
cates which contexts have interrupted.
Isochronous Transmit DMA Interrupt.
Indicates that one or
more isochronous transmit contexts have generated an interrupt.
This is not a latched event; it is the ORing of all bits in the isochro-
nous transmit interrupt event and isochronous transmit interrupt
mask registers. The isochronous transmit interrupt event register
indicates which contexts have interrupted.
Indicates that a packet was sent to an asynchronous receive
response context buffer and the descriptor’s xferStatus and
resCount fields have been updated.
Indicates that a packet was sent to an asynchronous receive
request context buffer and the descriptor’s xferStatus and
resCount fields have been updated.
Asynchronous Receive Response DMA Interrupt.
This bit is
conditionally set upon completion of an ARRS DMA context
command descriptor.
Asynchronous Receive Request DMA Interrupt.
This bit is
conditionally set upon completion of an ARRQ DMA context
command descriptor.
Asynchronous Response Transmit DMA Interrupt.
This bit is
conditionally set upon completion of an ATRS DMA command.
Asynchronous Request Transmit DMA Interrupt.
This bit is
conditionally set upon completion of an ATRQ DMA command.
8
postedWriteErr
RSCU
7
isochRx
RSCU
6
isochTx
RSCU
5
RSPkt
RSCU
4
RQPkt
RSCU
3
ARRS
RSCU
2
ARRQ
RSCU
1
respTxComplete
RSCU
0
reqTxComplete
RSCU
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW32306 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW323061394A | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW-33-01-G-D-200-065 | 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk |
| FW-33-01-L-D-200-075 | 制造商:Samtec Inc 功能描述:.050'' BOARD SPACERS - Bulk |
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