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參數(shù)資料
| 型號： | FW323 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口 |
| 文件頁數(shù)： | 138/152頁 |
| 文件大?。?/td> | 1625K |
| 代理商： | FW323 |
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138
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Crystal Selection Considerations
The FW323 is designed to use an external 24.576 MHz crystal connected between the XI and XO terminals to pro-
vide the reference for an internal oscillator circuit. IEEE1394a-2000 standard requires that FW323 have less than
±100 ppm total variation from the nominal data rate, which is directly influenced by the crystal. To achieve this, it is
recommended that an oscillator with a nominal 50 ppm or less frequency tolerance be used.
The total frequency variation must be kept below
±
100 ppm from nominal with some allowance for error introduced
by board and device variations. Trade-offs between frequency tolerance and stability may be made as long as the
total frequency variation is less than
±
100 ppm.
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (C
L
) is a function of not only the discrete load capacitors, but also
capacitances from the FW323 board traces and capacitances of the other FW323 connected components.The val-
ues for load capacitors (C
A
and C
B
) should be calculated using this formula:
C
A
= C
B
= (C
L
– C
stray
)
×
2
Where:
C
L
= load capacitance specified by the crystal manufacturer
C
stray
= capacitance of the board and the FW323, typically 2 pF—3 pF
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW323 PLL. The crystal and two-load capacitors should be considered as a unit during
layout. They should be placed as close as possible to one another, while minimizing the loop area created by the
combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possi-
ble to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the X1 and X0 sig-
nals.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 121. Absolute Maximum Ratings
* Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ), where V
I
max = 5.5 V.
Parameter
Symbol
Min
Max
Unit
Supply Voltage Range
Input Voltage Range*
Output Voltage Range at Any Output
Operating Free Air Temperature
Storage Temperature Range
V
DD
V
I
V
O
T
A
T
stg
3.0
0.5
0.5
0
–65
3.6
V
V
V
°
C
°
C
V
DD
+ 0.5
V
DD
+ 0.5
70
150
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