參數(shù)資料
型號(hào)： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁(yè)數(shù)： 8/152頁(yè)
文件大?。?/td> 1625K
代理商： FW323
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8
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
FW323 Functional Description
(continued)
(PMEs). When the FW323 is in a low-power state,
PMEs provide a hardware mechanism for requesting a
software wake-up. Together, the power management
register interface and PME support within the FW323
combine to form an efficient means for implementing
power management.
Isochronous Data Transfer
The isochronous data transfer logic handles the transfer
of isochronous data between the link core and the PCI
interface module. It consists of the isochronous register
module, the isochronous transmit DMA module, the
isochronous receive DMA module, the isochronous
transmit FIFO, and the isochronous receive FIFO.
Isochronous Register
The isochronous register module operates on PCI slave
accesses to OHCI registers within the isochronous
block. The module also maintains the status of inter-
rupts generated within the isochronous block and sends
the isochronous interrupt status to the OHCI interrupt
handler block.
Isochronous Transmit DMA (ITDMA)
The isochronous transmit DMA module moves data
from host memory to the link core, which will then send
the data to the 1394 bus. It consists of isochronous
contexts, each of which is independently controlled by
software, and can send data on a 1394 isochronous
channel.
During each 1394 isochronous cycle, the ITDMA
module will service each of the contexts and attempt to
process one 1394 packet for each context. If a context
is active, ITDMA will request access to the PCI bus.
When granted PCI access, a descriptor block is
fetched from host memory. This data is decoded by
ITDMA to determine how much data is required and
where in host memory the data resides. ITDMA
initiates another PCI access to fetch this data, which is
placed into the transmit FIFO for processing by the link
core. If the context is not active, it is skipped by ITDMA
for the current cycle.
After processing each context, ITDMA writes a cycle
marker word in the transmit FIFO to indicate to the link
core that there is no more data for this isochronous
cycle. As a summary, the major steps for the FW323
ITDMA to transmit a packet are the following:
1. Fetch a descriptor block from host memory.
2. Fetch data specified by the descriptor block from
host memory and place it into the isochronous
transmit FIFO.
3. Data in FIFO is read by the link and sent to the PHY
core device interface.
Isochronous Receive DMA (IRDMA)
The isochronous receive DMA module moves data
from the receive FIFO to host memory. It consists of
isochronous contexts, each of which is independently
controlled by software. Normally, each context can
process data on a single 1394 isochronous channel.
However, software can select one context to receive
data on multiple channels.
When IRDMA detects that the link core has placed data
into the receive FIFO, it immediately reads out the first
word in the FIFO, which makes up the header of the
isochronous packet. IRDMA extracts the channel
number for the packet and packet filtering controls from
the header. This information is compared with the
control registers for each context to determine if any
context is to process this packet.
If a match is found, IRDMA will request access to the
PCI bus. When granted PCI access, a descriptor block
is fetched from host memory. The descriptor provides
information about the host memory block allocated for
the incoming packet. IRDMA then reads the packet
from the receive FIFO and writes the data to host
memory via the PCI bus.
If no match is found, IRDMA will read the remainder of
the packet from the receive FIFO, but not process the
data in any way.
Asynchronous Data Transfer
The ASYNC block is functionally partitioned into two
independent logic blocks for transmitting and receiving
1394 packets. The ASYNC_TX unit is responsible for
packet transmission while the ASYNC_RX unit pro-
cesses received data.
Asynchronous Register
The asynchronous register module operates on PCI
slave accesses to OHCI registers within the asynchro-
nous block. The module also maintains the status of
interrupts generated within the asynchronous block
and sends the asynchronous interrupt status to the
OHCI interrupt handler block.
相關(guān)PDF資料
PDF描述
FW32305 1394A PCI PHY/Link Open Host Controller Interface
FW352
FW501 TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 7A I(D) | SO
FW801A Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device
FW801A-DB Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FW32305 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface
FW32306 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW323061394 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW323061394A 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW-33-01-G-D-200-065 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk
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