參數(shù)資料
型號： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù)： 43/152頁
文件大?。?/td> 1625K
代理商： FW323
Agere Systems Inc.
43
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
OHCI Registers
The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a
2 Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space.
These registers are the primary interface for controlling the FW323 IEEE 1394 OHCI function. This section
provides the register interface and bit descriptions. There are several set and clear register pairs in this
programming model, which are implemented to solve various issues with typical read-modify-write control
registers. There are two addresses for a set/clear register: RegisterSet and RegisterClear. Refer to Table 33 for
an illustration. A 1 bit written to RegisterSet causes the corresponding bit in the set/clear register to be set, while a
0 bit leaves the corresponding bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the
set/clear register to be reset, while a 0 bit leaves the corresponding bit in the set/clear register unaffected.
Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register.
However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The
interrupt event register is an example of this behavior. The following register definitions are based on version 1.0
of the 1394 Open Host Controller Specification. These definitions do not include any incremental changes or
additions defined in version 1.1 of the 1394 Open Host Controller Specification The version 1.1 changes and
additions will be included in a future revision of this data sheet.
Table 33. OHCI Register Map
DMA Context
—
Register Name
OHCI version
Global unique ID ROM
Asynchronous transmit retries
CSR data
CSR compare data
CSR control
Configuration ROM header
Bus identification
Bus options
Global unique ID high
Global unique ID low
PCI subsystem identification
Reserved
Configuration ROM map
Posted write address low
Posted write address high
Vendor identification
Capability ID and next item pointer
Power management
capabilities
Power management control and status
Power management extensions
Reserved
Host controller control
Abbreviation
Version
GUID_ROM
ATRetries
CSRData
CSRCompareData
CSRControl
ConfigROMhdr
BusID
BusOptions
GUIDHi
GUIDLo
SSID
—
ConfigROMmap
PostedWriteAddressLo
PostedWriteAddressHi
VendorID
CAP_ID
PM_CAP
Offset
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
46h
PMCSR
PM_Ext
—
HCControlSet
HCControlClr
—
—
48h
4Ah
4Ch
50h
54h
58h
5Ch
Reserved
Reserved
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