參數(shù)資料
型號(hào)： FW80200M733
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 10/36頁(yè)
文件大?。?/td> 461K
代理商： FW80200M733
Intel
80200 Processor based on Intel
XScale
Microarchitecture
Functional Overview
10
August 2002
Datasheet
2.6
Data Cache (D-Cache)
The D-Cache can contain high-use data such as lookup tables and filter coefficients, allowing the
core access to data at core frequencies. This prevents core stalls caused by multicycle accesses to
external memory.
The 32 KByte d-cache is 32-set/32-way associative, where each set contains 32-ways and each
way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty
bits (one for each of two 8-byte groupings in a line), and one valid bit. For each of the 32 sets,
0-28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via a
round robin policy.
The d-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within
the descriptors contained in the DTLB of the DMMU provide significant control over an enabled
d-cache. These bits specify cache operating modes such as read and write allocate, write-back,
write-through, and d-cache versus mini-data cache targeting
The d-cache (and mini-data cache) work with the load buffer and pend buffer to provide
“hit-under- miss” capability that allows the core to access other data in the cache after a “miss” is
encountered (see
Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page 11
for more
information). The d-cache (and mini-data cache) works in conjunction with the write buffer for
data that is to be stored to memory (see
Section 2.9, “Write Buffer (WB)” on page 11
for more
information).
2.7
Mini-Data Cache
The Mini-data Cache can contain frequently changing data streams such as MPEG video, allowing
the core access to data streams at core frequencies. This prevents core stalls caused by multicycle
accesses to external memory. The mini-data cache relieves the d-cache of data “thrashing” caused
by frequently changing data streams.
The 2 KByte mini-data cache is 32-set/2-way associative, where each set contains 2-ways and each
way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty
bits (one for each of two 8-byte groupings in a line), and a valid bit. The mini-data cache uses a
round robin replacement policy, and cannot be locked.
The mini-data cache (together with the d-cache) can be enabled or disabled. Attribute bits
contained within a coprocessor register specify operating modes write and/or read allocate,
write-back, and write-through.
The mini-data cache (and d-cache) work with the load buffer and pend buffer to provide
“hit-under-miss” capability that allows the core to access other data in the cache after a “miss” is
encountered (see
Section 2.8, “Fill Buffer (FB) and Pend Buffer (PB)” on page 11
for more
information). The mini-data cache (and d-cache) works in conjunction with the write buffer for
data that is to be stored to memory (see
Section 2.9, “Write Buffer (WB)” on page 11
for more
information).
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