- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370260 > FW80200M733 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | FW80200M733 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | FW80200M733 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
Intel
80200 Processor based on Intel
XScale
Microarchitecture
Package Information
16
August 2002
Datasheet
Table 5.
JTAG Pins
Name
Count
Type
Description
TCK
1
I
TEST CLOCK
is an input which provides the clocking function for
the IEEE 1149.1 Boundary Scan Testing (JTAG). State information
and data are clocked into the component on the rising edge and
data is clocked out of the component on the falling edge.
TDI
1
I
TEST DATA INPUT
is the serial input pin for the JTAG feature. TDI
is sampled on the rising edge of
TCK
, during the SHIFT-IR and
SHIFT-DR states of the Test Access Port. This signal has a weak
internal pullup to ensure proper operation when this signal is
unconnected.
TDO
1
O
TEST DATA OUTPUT
is the serial output pin for the JTAG feature.
TDO
is driven on the falling edge of
TCK
during the SHIFT-IR and
SHIFT-DR states of the Test Access Port. At other times,
TDO
floats.
TRST#
1
I
TEST RESET
asynchronously resets the Test Access Port (TAP)
controller function of IEEE 1149.1 Boundary Scan Testing (JTAG).
This signal has a weak internal pullup to ensure proper operation
when this signal is unconnected.
TRST#
must be driven low during processor reset to ensure proper
operation. Additionally, before performing JTAG test, the processor
should be reset and should have a valid clock at
CLK
to ensure it
does not enter a low-power mode.
TMS
1
I
TEST MODE SELECT
is sampled at the rising edge of
TCK
to
select the operation of the test logic for IEEE 1149.1 Boundary
Scan testing. This signal has a weak internal pullup to ensure
proper operation when this signal is unconnected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW802 | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A-DB | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW802C-DB | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW80200M733 S L678 | 制造商:Intel 功能描述:MPU 80200 Processor 32-Bit 0.18um 733MHz 241-Pin BGA |
| FW80200M733SL678 | 功能描述:IC I/O PROCESSOR 733MHZ 241-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| FW80219M400 S L7CL | 制造商:Intel 功能描述:PCI Processor 544-Pin BGA1 |
| FW80219M400SL7CL | 功能描述:IC MPU 32-BIT PCI XSCALE 544BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| FW80219M600SL7CM | 功能描述:IM MPU 32-BIT PCI XSCALE 544BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:60 系列:SCC 處理器類型:Z380 特點:全靜電 Z380 CPU 速度:20MHz 電壓:5V 安裝類型:表面貼裝 封裝/外殼:144-LQFP 供應(yīng)商設(shè)備封裝:144-LQFP 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。