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參數(shù)資料
| 型號(hào)： | FW802 |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大小： | 461K |
| 代理商： | FW802 |
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Intel
80200 Processor based on Intel
XScale
Microarchitecture
Package Information
Datasheet
August 2002
15
HOLD
1
I
HOLD
: Requests the Intel
80200 processor to float shared bus
signals.
IRQ#
1
I
Interrupt Request
: When IRQs are enabled, the processor
responds to a low level on this input by taking the IRQ interrupt
exception.
LOCK/LEN[1]
1
O
Rst(X)
Hld(Z)
Slp(X)
Atomic Transaction Indicator/Length
:
During the first cycle of the issue phase, this signal indicates the
current transaction is part of an atomic read-write pair.
During the second cycle of the issue phase, this signal is the
middle bit of a value which indicates the length of the transaction.
LOWVPP
1
I
Pad Voltage Level:
When tied to the same level as V
, indicates
voltage for the device pins (V
) is less than 2.5V. When tied to
V
, indicates voltage at the device pins is greater than or equal to
2.5V.
LOWVCC
1
I
Core Voltage Level:
When tied to the same level as V
,
indicates voltage for the core (V
) is less than 1.0V. When tied to
V
SS
, indicates voltage for the core is greater than or equal to 1.0V.
MCLK
1
I
Memory Clock
: all bus signals must be synchronous to this clock.
N/C
8
N/C
NO CONNECT
. Do not make electrical connections to these balls.
PLLCFG
(Config. Pin)
1
I
PLL Configuration:
While RESET# is asserted, this pin is
sampled by the 80200 to select the initial clock multiplier value.
When tied high, the initial clock multiplier is 6. When tied low, the
initial clock multiplier is 3. This signal must be tied to a valid level at
all times. When using the Intel 80312 I/O companion chip, this
signal must be tied high.
PWRSTATUS[1:
0]
2
O
Rst(0)
Hld(Q)
Slp(Q)
Power Status Indicator
: Indicates the current power mode of the
Intel
80200 processor
.
This signal contains an encoded value to
indicate the current power state:
00 for Normal
01 for Idle
10 for Reserved (Do Not Use)
11 for Sleep
RESET#
1
I
Reset
: When asserted, this signal resets the processor. This signal
must be asserted for at least 32 consecutive MCLK cycles to
achieve a valid reset.
RESETOUT#
1
O
Rst(0)
Hld(Q)
Slp(1)
Reset Status Output
: This signal is asserted when the processor
detects
RESET#
, and deasserts when the processor has
completed resetting.
W_R#/LEN[0]
1
O
Rst(X)
Hld(Z)
Slp(X)
Address Strobe/Length
:
During the first cycle of the issue phase, this signal indicates that
the current transaction is a read (
W_R#
= 0) or a write (
W_R#
= 1).
During the second cycle of the issue phase, this signal is the LSB
of a value which indicates the length of the transaction.
1. For signals
D
,
DCB
,
BE#
during Hold mode, these continue to carry valid data until all pending transactions from the 80200
have been completed. Then these signals float.
Table 4.
Signal Pin Description (Sheet 2 of 2)
Name
Count
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW802A | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802A-DB | Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW802C | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW802C-DB | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| FW803-09-DB | PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW80200M400 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| FW80200M400SL676 | 功能描述:IC I/O PROCESSOR 400MHZ 241-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| FW80200M600 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| FW80200M600 S L677 | 制造商:Intel 功能描述:MPU 80200 Processor 32-Bit 0.18um 600MHz 241-Pin BGA |
| FW80200M600 SL677 | 制造商:Intel 功能描述: |
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