參數(shù)資料
型號(hào)： FW802
英文描述： Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
中文描述： 低功耗PHY的IEEE 1394A端口- 2000兩線收發(fā)器/仲裁器裝置
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 461K
代理商： FW802
Intel
80200 Processor based on Intel
XScale
Microarchitecture
About this Document
Datasheet
August 2002
5
1.0
About this Document
This is the Advance Information data sheet for the Intel
80200 processor based on Intel
XScale
microarchitecture (ARM* architecture compliant). This data sheet contains a functional overview,
mechanical data (package signal locations and simulated thermal characteristics), targeted
electrical specifications (simulated), and bus functional waveforms. Detailed functional
descriptions other than parametric performance is published in the
Intel
80200 Processor based
on Intel
XScale
Microarchitecture Developer’s Manual
.
2.0
Functional Overview
The Intel
80200 processor technology is compliant with the ARM* Version 5TE instruction set
architecture (ISA). The Intel
80200 processor is designed with Intel state-of-the-art 0.18 micron
production semiconductor process technology. This process technology, along with the
compactness of the ARM RISC ISA, enables the Intel
80200 processor to operate over a wide
speed/power range, producing industry-leading mW/MIPS performance.
7-8 stage Superpipeline promotes high speed, efficient core performance
128-entry Branch Target Buffer keeps pipeline filled with statistically correct branch choices
32-entry Instruction Memory Management Unit for logical-to-physical address translation,
access permissions, I-Cache attributes
32-entry Data Memory Management Unit for logical-to-physical address translation, access
permissions, D-Cache attributes
32 KB Instruction Cache can hold entire programs, preventing core stalls caused by multicycle
memory accesses
32 KB Data Cache reduces core stalls caused by multicycle memory accesses
2 KB Minidata Cache for frequently changing data streams avoids “thrashing” of the D-Cache
4-entry Fill and Pend Buffers promote core efficiency by allowing “hit-under- miss” operation
with Data Caches
Power Management Unit gives power savings via idle, and sleep modes
8-entry Write Buffer allows the core to continue execution while data is written to memory
Multiply-Accumulate Coprocessor can do two simultaneous 16-bit SIMD multiplies with
40-bit accumulation for efficient, high quality audio
Table 1.
Related Documentation
Document Title
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80200 Processor based on Intel
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相關(guān)PDF資料
PDF描述
FW802A Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
FW802A-DB Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device
FW802C FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
FW802C-DB FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE
FW803-09-DB PHY IEEE 1394A Three-Cable Transceiver/Arbiter Device
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