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參數(shù)資料
| 型號： | FW802C |
| 英文描述： | FW 802C LOW - POWER IEEE 1394A-2000 TWO CABLE TRANSCEIVER/ ARBITER DEVICE |
| 中文描述： | 防火墻802C低-動力IEEE 1394A端口- 2000兩艘電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 301K |
| 代理商： | FW802C |
12
Agere Systems Inc.
Data Sheet, Rev. 1
October 2002
Two-Cable Transceiver/Arbiter Device
FW802C Low-Power PHY IEEE1394A-2000
Crystal Selection Considerations
(continued)
Load Capacitance
The frequency of oscillation is dependent upon the load capacitance specified for the crystal, in parallel resonant
mode crystal circuits. Total load capacitance (C
L
) is a function of not only the discrete load capacitors, but also
capacitances from the FW802C board traces and capacitances of the other FW802C connected components.
The values for load capacitors (C
A
and C
B
) should be calculated using this formula:
C
A
= C
B
= (C
L
– C
stray
)
×
2
Where:
C
L
= load capacitance specified by the crystal manufacturer
C
stray
= capacitance of the board and the FW802C, typically 2—3 pF
Board Layout
The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency and minimizing
noise introduced into the FW802C PLL. The crystal and two load capacitors should be considered as a unit during
layout. They should be placed as close as possible to one another, while minimizing the loop area created by the
combination of the three components. Minimizing the loop area minimizes the effect of the resonant current that
flows in this resonant circuit. This layout unit (crystal and load capacitors) should then be placed as close as possi-
ble to the PHY XI and XO terminals to minimize trace lengths. Vias should not be used to route the XI and XO sig-
nals.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 2. Absolute Maximum Ratings
* Except for 5 V tolerant I/O (CTL0, CTL1, D0—D7, and LREQ) where V
I
max = 5.5 V.
Parameter
Symbol
Min
Max
Unit
Supply Voltage Range
Input Voltage Range*
Output Voltage Range at Any Output
Operating Free Air Temperature
Storage Temperature Range
V
DD
V
I
V
O
T
A
T
stg
3.0
0.5
0.5
0
–65
3.6
V
V
V
°
C
°
C
V
DD
+ 0.5
V
DD
+ 0.5
70
150
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