參數(shù)資料
型號(hào): GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù): 14/90頁(yè)
文件大小: 647K
代理商: GPTRM
MOTOROLA
1-2
FUNCTIONAL OVERVIEW
GPT
REFERENCE MANUAL
If not needed for timing functions, any of the GPT pins can be used for general-pur-
pose input/output (I/O). The input capture and output compare pins are bidirectional
and can be used to form an 8-bit parallel port. The PWM pins are outputs only. The
pulse accumulator input (PAI) and PCLK pins are inputs only.
The GPT bus interface provides the connection to the intermodule bus (IMB). This bus
provides a standard interface between different modules and the CPU. Important fea-
tures of the bus include multiple bus masters, exception processing support, address
space partitioning, multiple interrupt levels, vectored interrupts, and extendable (wait
states) bus cycles. New modules designed to conform to the IMB protocol can quickly
be combined with other processors, peripherals, and memories to meet almost any
controller application.
Table 1-1
word boundaries; however, all registers and counters can be accessed using byte or
word operations. Counters TCNT and PWMCNT, and registers TICx, TOCx, and TI4/
O5 must be accessed by word operations to ensure coherency. Coherency is the read-
ing or writing of data identical in age. Using byte accesses when reading a counter
such as the TCNT, there is a possibility that data in the byte not being accessed will
change while the other byte is read. To prevent this, both bytes must be accessed at
the same time.
shows the registers and counters in the GPT. The addresses shown are on
Two control registers, the module configuration register (MCR) and the interrupt con-
trol register (ICR) can only be accessed while the processor is in supervisor mode. Re-
fer to
SECTION 7 INTERRUPTS
and
SECTION 9 SPECIAL MODES
on these registers.
for information
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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