參數(shù)資料
型號(hào)： GPTRM
英文描述： General-Purpose Timer Reference Manual
中文描述： 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù)： 25/90頁(yè)
文件大?。?/td> 647K
代理商： GPTRM
GPT
REFERENCE MANUAL
COMPARE/CAPTURE UNIT
MOTOROLA
3-3
3.2 Input Capture Functions
Each GPT input capture pin (IC1, IC2, IC3, and also IC4/OC5) when used as an input
capture function, has a dedicated 16-bit latch, input edge-detection/selection logic,
and interrupt generation logic. All of the input capture functions use the same 16-bit
timer counter (TCNT). The latch captures the contents of the TCNT when the selected
event occurs at the corresponding input capture pin. Refer to
1.2 Input Capture (IC)
Concepts
for additional information on the basic operation of an input capture func-
tion. The edge detection logic contains control bits which allow user software to select
the edge polarity to be recognized. These are the EDGExA and EDGExB bits in timer
control register 2 (TCTL2). Each of the input capture functions can be independently
configured to detect rising edges only, falling edges only, any edge (rising or falling),
or disable the input capture function. Refer to
Figure 3-5
and
Table 3-1
for the re-
quired bit patterns. The input capture functions operate independently of each other
and can capture the same TCNT value if the input edges are all detected within the
same timer count cycle.
The interrupt generation logic includes a status flag, which indicates that an edge is
detected, and a local interrupt enable bit, which determines if the corresponding input
capture function will generate a hardware interrupt request. The input capture sets the
ICxF bit in the timer interrupt flag register 1(TFLG1) and can cause an interrupt if the
corresponding ICxI bit is set in the timer interrupt mask register 1 (TMSK1). If the in-
terrupt request is inhibited (the ICxI bit cleared), the input capture is operating in polled
mode where software must read the status flag to recognize that an edge was detect-
ed. Refer to
7.1 Interrupts
for additional details on interrupt operation.
Because input capture events are generally asynchronous to the timer counter, they
are conditioned by a synchronizer and digital filter. This synchronizes the input events
to the system clock so that actual latching of the TCNT contents will occur on the op-
posite half cycle of the system clock from when the counter is being incremented. The
input is conditioned in such a way that any event longer than two system clocks is
guaranteed to be captured and any signal shorter than one system clock will be filtered
out and have no effect. Notice the relationship of the system clock to the output of the
synchronizer as shown in
Figure 3-2
. The value latched into the capture register by
an input capture corresponds to the value of the counter several system clock cycles
after the input transition which triggered the edge detection logic. There can be up to
one clock cycle of uncertainty in latching of the input transition. The maximum time is
determined by the system clock frequency.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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