參數(shù)資料
型號(hào): GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù): 48/90頁(yè)
文件大小: 647K
代理商: GPTRM
MOTOROLA
7-2
INTERRUPTS
GPT
REFERENCE MANUAL
NOTE
If two or more modules have the same arbitration ID and generate an
interrupt at the same priority level, unpredictable operation can oc-
cur.
An ID of zero disables the module from arbitrating for the interrupt, and if the module
does generate an interrupt and the CPU mask level is set at a lower value, a spurious
interrupt exception is generated. Refer to the appropriate CPU manual for a discussion
of exception processing. Refer to
SECTION 9 SPECIAL MODES
for additional details
about the MCR.
* Refer to
SECTION 9 SPECIAL MODES
for information on these bits.
Figure 7-1 ARB Bits of MCR
IARB [3:0] — Interrupt Arbitration ID
System software must set this field between $F–$1; $F is the highest priority. This field
is initialized to zero during reset, which disables arbitration and causes interrupts gen-
erated by the GPT to be treated as spurious.
Figure 7-2 GPT Interrupt Vector Generation
For simultaneous interrupts, a hard-wired priority scheme is implemented. This
scheme assures that the vector returned to the CPU will point to the interrupt with the
highest priority. Refer to
Table 7-1
for the priority arrangement, along with the associ-
ated vector address for each channel. Hardware prevents the vector from changing
(due to a new interrupt) while it is being driven out on the IMB.
MCR —
Module Configuration Register
$YFF900
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STOP*
FRZ1*
FRZ0*
STOPP*
INCP*
0
0
0
SUPV*
0
0
0
IARB3
IARB2
IARB1
IARB0
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
INTERRUPT
MASKS
INTERRUPT
REQUEST
LEVEL
INTERRUPT
LEVEL
ENCODER
INTERRUPT
PRIORITY
ENCODER
INTERRUPT
ENABLE
LOGIC
MODULE
INTERRUPT
VECTOR
INTERRUPT
SOURCE
NUMBER
IIRQ [7:1]
4 LSN
4 MSN
PRIORITY
ADJUST BITS
VECTOR
BASE ADDRESS
4
4
11
11
3
7
INTERRUPT
SOURCES
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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