參數(shù)資料
型號(hào): GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時(shí)器參考手冊(cè)
文件頁數(shù): 35/90頁
文件大?。?/td> 647K
代理商: GPTRM
GPT
REFERENCE MANUAL
PULSE ACCUMULATOR
MOTOROLA
4-3
4.1.1 Pulse Accumulator Register/Pulse Accumulator Counter (PACTL/PACNT)
The PACTL register (
Figure 4-2
) is used to select the operational mode of the pulse
accumulator. PACNT is the pulse accumulator 8-bit counter. Control bit I4/O5 config-
ures input capture 4/output compare 5 pin as an input capture or output compare. Re-
fer to
3.4 Input Capture 4/Output Compare 5 (IC4/OC5)
.
*Refer to
3.4 Input Capture 4/Output Compare 5 (IC4/OC5)
for information on this bit.
NOTE: The address shown is on a word boundary; however, the register can be accessed by a word or byte cycle.
Figure 4-2 Pulse Accumulator Control Register/Pulse Accumulator Counter
(PACTL/PACNT)
PAIS — PAI Pin State (Read-Only)
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
PAMOD — Pulse Accumulator Mode
0 = External event counting
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings based on the state of the PAMOD bit.
PCLKS — PCLK Pin State (Read-Only)
I4/O5 — Input Capture 4/Output Compare 5
0 = Output compare 5 function enabled
1 = Input capture 4 function enabled
Refer to
3.4 Input Capture 4/Output Compare 5 (IC4/OC5)
for details on the opera-
tion of this function.
PACTL/PACNT —
Pulse Accumulator Control Register/Counter Register
$YFF90C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAIS
PAEN
PAMOD
PEDGE PCLKS
I4/O5*
PACLK1
PACLK0
PULSE ACCUMULATOR COUNTER
RESET:
U
0
0
0
U
0
0
0
0
0
0
0
0
0
0
0
Table 4-1 Pulse Accumulator Mode Select
PAMOD
0
0
1
1
PEDGE
0
1
0
1
Action on Clock
PAI falling edge increments counter.
PAI rising edge increments counter.
A zero on PAI inhibits counting (gated mode).
A one on PAI inhibits counting (gated mode).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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