參數(shù)資料
型號(hào): GPTRM
英文描述: General-Purpose Timer Reference Manual
中文描述: 通用定時(shí)器參考手冊(cè)
文件頁(yè)數(shù): 33/90頁(yè)
文件大?。?/td> 647K
代理商: GPTRM
GPT
REFERENCE MANUAL
PULSE ACCUMULATOR
MOTOROLA
4-1
SECTION 4 PULSE ACCUMULATOR
4.1 Pulse Accumulator
The pulse accumulator counter (PACNT) is an 8-bit read/write up counter register that
can operate in an external event counting or gated time accumulation mode. The bits
in the pulse accumulator control register (PACTL); control the operation of PACNT. In
the event counting mode the counter increments each time a selected edge (PEDGE
bit) on the pulse accumulator input (PAI) pin is detected.
Figure 4-1
shows a block di-
agram of the pulse accumulator.
Because the PACNT register can be accessed at any time, a value representing the
number of edges to be counted can be written to it. As the edges are counted the
counter will approach $FF and finally roll over to $00. If interrupts are enabled, an over-
flow interrupt will be generated.
The maximum clocking rate is the system clock divided by four. In the gated time ac-
cumulation mode there are four clock sources available. Bits PACLK[1:0] select which
of these sources will be used. The selected clock increments the PACNT when PAI is
in the active state. The PAMOD and PEDGE control bits (
Table 4-1
) determine the ac-
tive state. Refer to
Table 4-2
for the bit patterns and clocks available to the pulse ac-
cumulator.
The PACTL and PACNT registers are implemented as one 16-bit register, but may be
accessed with byte or word access cycles. Both registers are cleared at reset, but the
PAIS and PCLKS bits will show the state of the PAI and PCLK pins, respectively.
Two maskable interrupts are available from the pulse accumulator. The pulse accu-
mulator overflow flag indicates that the pulse accumulator count has rolled over from
$FF to $00. This can be used to extend the range of the counter beyond eight bits.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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