參數(shù)資料
型號(hào): GS8150V36AB-300IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K X 36 LATE-WRITE SRAM, 1.6 ns, PBGA119
封裝: FBGA-119
文件頁數(shù): 22/25頁
文件大?。?/td> 885K
代理商: GS8150V36AB-300IT
GS8150V18/36AB-357/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.08 9/2008
6/25
2003, GSI Technology
Register-Register Late Write, Pipelined Read Truth Table
CK
ZZ
SS
SW
Bx
G
Current Operation
DQ
(tn)
DQ
(tn+1)
X
1
X
Sleep (Power Down) mode
Hi-Z
0
1
X
Deselect
***
Hi-Z
0
1
X
1
Read
Hi-Z/
Hi-Z
0
1
X
0
Read
***
Q(tn)
0
X
Write All Bytes
***
D(tn)
0
X
Write Bytes with Bx = 0
***
D(tn)
0
1
X
Write (Abort)
***
Hi-Z
Notes:
1. If one or more Bx = 0, then B = “T” else B = “F”.
2. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”.
3. “***” indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation.
4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces
of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial exter-
nal (base) address.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8150V36AB-333 制造商:GSI Technology 功能描述:GS8150V36AB-333 - Trays
GS8150V36AB-333I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
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GS8150V36AB-357I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS8150V36AGB-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM