參數(shù)資料
型號(hào)： GS9023ACFY
廠商： Gennum Corporation
元件分類： Codec
英文描述： GENLINX -TM II GS9023A Embedded Audio CODEC
中文描述： GENLINX -商標(biāo)二GS9023A嵌入式音頻編解碼器
文件頁(yè)數(shù)： 18/37頁(yè)
文件大小： 318K
代理商： GS9023ACFY
18 of 37
G
GENNUM CORPORATION
19795 - 6
2.1.10 Arbitrary Data Packets
The GS9023A is capable of multiplexing arbitrary data
packets according to SMPTE 291M. Typically, this consists
of linear time code data (LTC), vertical interval time code
data (VITC) or other data which is multiplexed once per
field. The user must input the 9 LSBs starting from the
secondary data identification (SDID) word to the last user
data word (UDW) of the ancillary data packet containing
arbitrary data. The CS word and bit 10 of all words in the
packet are internally generated.
The arbitrary data packet data ID is configured in
“PKTID[7:0]” of Host Interface Register #5h. To process
arbitrary data, the user must set the “PKON” bit of Host
Interface Register #1h. Also, the user must specify the line
number in “PKTLINE[7:0]” in Host Interface Register #9h.
This value corresponds to the line in video field 1 in which
the user wants the arbitrary data packet to be multiplexed.
The corresponding line in field 2 is automatically selected
for arbitrary data packet multiplexing. Arbitrary data is
typically multiplexed during the active portion of the line in
the vertical blanking interval (VBI). Care should be taken to
avoid selecting a line in the active picture. Table 11 lists
recommended multiplexing lines according to the video
standard.
NOTE: In field #1, the line number is offset by one from the
value configured in “PKTLINE[7:0]”.Arbitrary data is input to
the GS9023A as shown in Figure 11. The data is stored in
an internal arbitrary data packet buffer which is cleared at
the end of every field. Arbitrary data must be written to the
buffer before the line number specified in “PKTLINE[7:0]” is
reached in order for the packet to be multiplexed. Data is
input to the PKT[8:0] pins and clocked in on the rising edge
of PCLK. PKTEN must be set HIGH one PCLK cycle before
the data at the PKT[8:0] inputs is valid. PKTEN must go
LOW one PCLK cycle before the last user data word (UDW)
is input to the PKT[8:0] inputs. Parity (bit 8) for each UDW
can be enabled by setting the “PKTPRTY” bit of Host
Interface Register #8h to HIGH. When “PKTPRTY” is HIGH,
data input at PKT[8] is overwritten by the parity bit.
Up to 255 words (253 UDWs + SDID + DC) can be input
and multiplexed once per field.
The arbitrary data packet structure as described in SMPTE
291M is shown in Figure 11.
Figure 11 Arbitrary Data Packet Input Timing Diagram
TABLE 11 MULTIPLEX POSITION FOR ARBITRARY DATA PACKET
VIDEO STANDARD
RECOMMENDED
MULTIPLEX LINE
HORIZONTAL STARTING
POSITION (WORD #)
HORIZONTAL ENDING
POSITION (WORD #)
525/D2
9/272
340
360
525/D1
14/277
0
1439
525/16:9
14/277
0
1919
NOTE: 525/4:4:4:4 and all 625 line video standards are not supported.
* Horizontal Starting Position 0 is the first word of the active picture.
PCLK (I)
PKTEN (I)
1 clk
1 clk
Valid data
PKT[8:0] (I)
1 - The ancillary data flag, ADF, is one word in composite systems (ANSI/SMPTE 259M)
and three words in component systems (ANSI/SMPTE 125M).
2 - The ADF, DID and CHKSUM words are automatically generated by the GS9023A.
A
1
S
D
D
2
U
U
U
U
U
U
U
C
A
1
A
1
NOTE:
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