參數(shù)資料
型號(hào)： GS9023ACFY
廠商： Gennum Corporation
元件分類： Codec
英文描述： GENLINX -TM II GS9023A Embedded Audio CODEC
中文描述： GENLINX -商標(biāo)二GS9023A嵌入式音頻編解碼器
文件頁(yè)數(shù)： 31/37頁(yè)
文件大?。?/td> 318K
代理商： GS9023ACFY
31 of 37
G
GENNUM CORPORATION
19795 - 6
9h
0
ACCDBNERR
Audio control packet DBN error. A DBN discontinuity was detected.
NOTE: When a DBN discontinuity is detected, the VFLA/B pins remain
valid (LOW).
R
0
1
ACCDCERR
Audio control packet DC error. The number of UDW indicated does not
match the number of words found in the audio control packet.
R
0
3-2
RSV
Not used.
-
4
ACCB9ERR
Audio control packet inversion bit error. An incorrect bit 9 inversion of
bit 8 was detected in the audio control packet.
R
0
6-5
RSV
Not used.
-
7
A4B9ERR
Extended audio packet inversion bit error. An incorrect bit 9 inversion
of bit 8 was detected in the extended audio packet.
R
0
Ah
7-0
DELA/B[7:0]
Audio control packet delay. Designates the audio control packet delay
data as specified in the SMPTE 272M standard. DELA corresponds to
audio channels 1 and 2, while DELB is the corresponds to audio
channels 3 and 4. “DELA/B[25]” is the MSB and “DELA/B[0]” is the
LSB.
R
0
Bh
7-0
DELA/B[15:8]
R
0
Ch
7-0
DELA/B[23:16]
R
0
Dh
1-0
DELA/B[25:24]
R
0
2
ACSYNCA/B
Audio control packet synchronization data. Designates the sync mode
bits (asx, asy) as defined in SMPTE 272M (section 14.5) of channels 1/
2 or 3/4 of the audio control packet. The bits are selected by “AC34/
12”.
R
0
3
ACDLY
Audio control packet delay active. Designates the ‘e’ bit of word
“DELx0” of an audio control packet as defined in SMPTE 272 (section
14.7). When HIGH indicates valid audio delay data.
R
0
4
ACT1/2
Active channel 1/2 flag. Demultiplexed from the audio control packet,
when present.
R
0
5
ACT3/4
Active channel 3/4 flag. Demultiplexed from the audio control packet,
when present.
R
0
6
RSV
Not used.
-
7
AC34/12
Audio control packet and channel status channel pair select.
When set LOW, the audio control packet delay data for audio channels
1 and 2 is captured in registers #Ah, #Bh, #Ch and #Dh. Registers #Eh
and #Fh will display the channel status information for channels 1 and
2 respectively.
When set HIGH, the audio control packet delay data for audio
channels 3 and 4 is captured in registers #Ah, #Bh, #Ch and #Dh.
Registers #Eh and #Fh will display the channel status information for
channels 3 and 4 respectively.
R/W
0
TABLE 15 DEMULTIPLEX MODE HOST INTERFACE REGISTERS (CONTINUED)
ADDRESS
BIT
NAME
FUNCTION
R/W
DEFAULT
相關(guān)PDF資料
PDF描述
GS9023 Embedded Audio CODEC
GS9023-CFY Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk
GS9024 Automatic Cable Equalizer
GS9024-CKB Automatic Cable Equalizer
GS9024-CTB Automatic Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9023ACFYE3 制造商:Semtech Corporation 功能描述:Audio Codec 4ADC / 4DAC 24-Bit 100-Pin LQFP
GS9023B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Embedded Audio CODEC
GS9023BCVE3 功能描述:IC AUDIO CODEC 100PIN TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
GS9023-CFY 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Embedded Audio CODEC
GS9024 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Automatic Cable Equalizer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*