參數(shù)資料
型號(hào)： GS9023ACFY
廠商： Gennum Corporation
元件分類： Codec
英文描述： GENLINX -TM II GS9023A Embedded Audio CODEC
中文描述： GENLINX -商標(biāo)二GS9023A嵌入式音頻編解碼器
文件頁(yè)數(shù)： 25/37頁(yè)
文件大?。?/td> 318K
代理商： GS9023ACFY
25 of 37
G
GENNUM CORPORATION
19795 - 6
2.3 MULTIPLEX AND DEMULTIPLEX MODES
2.3.1 Delay of Video and Audio
The GS9023A can be configured for various audio sample
delays with respect to the video signal. The audio sample
delay is selected in “BUFSEL[1:0]” of Host Interface
Register #6h. Table 13 lists the various audio sample
delays.
2.3.2 Non-Standard Sample Distributions
Gennum Corporation has made every effort to maximize
compatibility of the GS9023A with other Embedded Audio
data
streams.
Unfortunately,
implementations (i.e. non-standard sample distributions)
Gennum cannot guarantee compatibility with all Embedded
Audio data streams.
due
to
variations
in
2.3.3 Host Interface
The Host Interface Registers allow for device configuration
and provide status information. The GS9023A contains
sixteen internal registers that are accessible through the
Host Interface. Based on the mode of operation the
registers have different functionality. In Multiplex Mode the
registers are defined in Table 14 and in Demultiplex Mode
the registers are defined in Table 15.
The asynchronous Host Interface consists of a 4 bit address
bus (ADDR[3:0]), 8 bit data bus (DATA[7:0]), read enable
(RE), write enable (WE) and chip select (CS). The Host
Interface access is independent of the PCLK or ACLK
inputs. Read and write cycle timing is detailed in Figure 19.
In a read cycle, CS is driven LOW t
AS
seconds after a valid
address. RE is then driven LOW after t
ACS
seconds for a
minimum of t
RD
seconds. After t
GQV
seconds, the address
register contents are output on the data bus. After a
minimum of t
RDH
seconds, CS is driven HIGH to end the
cycle.
Similarly, in a write cycle, CS is driven LOW t
AS
seconds
after a valid address. WE is then driven low after t
ACS
seconds
for a minimum of t
WD
seconds. Valid data must be
present for a minimum of t
DS
seconds
before WE is driven
HIGH again. After a minimum of t
WDH
seconds, CS is driven
HIGH to end the cycle.
2.3.4 Reset
Reset timing is detailed in Figure 20. Setting the RESET pin
to LOW for a period of t
RESET
seconds forces the audio
outputs LOW and re-initializes the internal control circuitry
including returning all Host Interface Register values to their
original default values. The RESET pin can be used for
synchronizing multiple devices.
2.3.5 Interconnection with GS9032 or GS7005
The user should pay special attention when laying out the
GS9023A to operate with the GS9032 or GS7005. The MSB
to LSB convention is consistent between the GS9023A and
GS9022 but reversed with respect to the GS9032 or
GS7005. Layout complexity can be minimized by placing
the GS9023A and the GS9032 or GS7005 on opposite sides
of the printed circuit board (PCB).
2.3.6 Audio Clock and Video Clock Stability in Multiplex Mode
Once the GS9023A is locked and processing audio, it is
recommended that the audio clock frequency (ACLK at
128fs) remains stable and locked to video clock (VCLK). If
VCLK is periodically switched or momentarily unstable, the
audio clock phase locked loop circuit external to the
GS9023A may be disrupted, causing ACLK to be at some
arbitrary frequency. Under these conditions, operation of
the GS9023A cannot be guaranteed and may result in
corrupted audio. This is due to possible overflow/underflow
condition occurring in the GS9023A internal FIFO, which is
caused by the unstable audio clock input. If an overflow/
underflow condition occurs, the “BUFSTAT” bit in Host
Interface Register #2h will be set HIGH. The internal FIFO
can be reset automatically by setting the “BUFCTRL” bit in
Host Interface Register #2h HIGH.
2.3.7 Interconnection with GS9020
The TRS_INSERT function of the GS9020 should be
disabled when operating with the GS9023A. This is
controlled through the Host Interface of the GS9020 and
through the CLIP_TRS pin. If enabled this may cause the
GS9020 to continue outputting valid TRS codes even when
the input signal is removed.The GS9023A may not detect
this loss of video input and could remain locked. When a
valid video signal is re-applied to the GS9020, the
GS9023A's internal audio buffers may not have been reset
and will therefore be in an overflow or underflow condition.
TABLE 13 AUDIO VIDEO DELAY
“BUFSEL[1:0]”
MODE
MULTIPLEX (US)
DEMULTIPLEX (US)
MULTIPLEX/DEMULTIPLEX
CONNECTION (US)
0
(70 Sample)
875
541
1416
1
(26 Sample - Default)
250
312
563
2
(20 Sample)
187
250
437
1. NOTE: When the video signal is in D2 format, the delay is fixed at 70 samples (1416 us).
相關(guān)PDF資料
PDF描述
GS9023 Embedded Audio CODEC
GS9023-CFY Aluminum Electrolytic Radial Leaded Bi-Polar Capacitor; Capacitance: 100uF; Voltage: 63V; Case Size: 12.5x20 mm; Packaging: Bulk
GS9024 Automatic Cable Equalizer
GS9024-CKB Automatic Cable Equalizer
GS9024-CTB Automatic Cable Equalizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9023ACFYE3 制造商:Semtech Corporation 功能描述:Audio Codec 4ADC / 4DAC 24-Bit 100-Pin LQFP
GS9023B 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Embedded Audio CODEC
GS9023BCVE3 功能描述:IC AUDIO CODEC 100PIN TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
GS9023-CFY 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Embedded Audio CODEC
GS9024 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Automatic Cable Equalizer
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*