參數(shù)資料
型號(hào)： GT-48006A
廠(chǎng)商： Galileo Technology Services, LLC
英文描述： Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器)
中文描述： 低成本雙口10/100Mbps以太網(wǎng)橋/開(kāi)關(guān)控制器（低成本，雙端口10/100以太網(wǎng)橋式/交換式控制器）
文件頁(yè)數(shù)： 10/33頁(yè)
文件大?。?/td> 352K
代理商： GT-48006A
GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
18
10.
MII Management Interface (SMI)
The GT-48006A MAC contains an MII Management Interface (SMI) for an MII compliant PHY devices. This allows con-
trol and status parameters to be passed between the GT-48006A and the PHY by one serial pin (MDIO) and a clocking
pin (MDC), reducing the number of control pins required for PHY mode control. Typically, the GT-48006A will continu-
ously query the PHY devices for their link status. The predefined PHY addresses for the link query are 1 and 2 (out of
possible 32 addresses).
10.1
SMI Cycles
The SMI protocol consists of a bit stream that is driven or sampled by the GT-48006A on each rising edge of the MDC
clock. The bit stream format of the SMI frame is described in Table 5.
PRE (Preamble). At the beginning of each transaction, the GT-48006A sends a sequence of 32 contiguous
logic one bits on MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use
to establish synchronization.
ST (Start of Frame). A Start of Frame pattern of 01.
OP (Operation Code). 10 - Read; 01 - Write
PhyAd (PHY Address). A 5 bit address of the PHY device (32 possible addresses). The first PHY address bit
transmitted by the GT-48006A is the MSB of the address.
RegAd (Register Address). A 5 bit address of the PHY register (32 possible registers in each PHY). The first
register address bit transmitted by the GT-48006A is the MSB of the address. The GT-48006A always queries
the PHY device for status of the link by reading register 1, bit 2.
TA (Turn Around). The turnaround time is a 2 bit time spacing between the Register Address field and the Data
field of the SMI frame to avoid contention during a read transaction. During a Read transaction the PHY should
not drive MDIO in the first bit time and drive ‘0’ in the second bit time. During a write transaction, the GT-
48006A drives a ‘10’ pattern to fill the TA time.
Data (Data). The data field is 16 bits long. The PHY drives the data field during Read transactions. The GT-
48006A drives the data field during write transactions. The first data bit transmitted and received shall be bit 15
of the PHY register being addressed.
IDLE (Idle). The IDLE condition on MDIO is a high impedance state. The MDIO driver is disabled and the PHY
should pull-up the MDIO line to a logic one.
10.1.1 SMI Timing Requirements
Figure 4 shows a waveform of the MDC line which is driven by the GT-48006A. Table 6 shows typical MDC timings.
Figure 4: GT-48006A MDC Waveform
Table 5: SMI Bit Stream Format
PRE
ST
OP
Ph y A d
Re g Ad
TA
Da t a
ID LE
READ
1...1
01
10
AAAAA
RRRRR
Z0
D..D(16)
Z
WRITE
1...1
01
AAAAA
RRRRR
10
D..D(16)
Z
t1
MDC
Vih
min
Vil
max
t2
t3
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