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參數(shù)資料
| 型號(hào)： | GT-48006A |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器) |
| 中文描述： | 低成本雙口10/100Mbps以太網(wǎng)橋/開關(guān)控制器（低成本，雙端口10/100以太網(wǎng)橋式/交換式控制器） |
| 文件頁數(shù)： | 6/33頁 |
| 文件大?。?/td> | 352K |
| 代理商： | GT-48006A |
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GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
14
9.
Fast Ethernet Interfaces
The GT-48006A interfaces directly to two MII (Media Independent Interface) ports which are compliant with the IEEE
standard (please see 802.3u Fast Ethernet standard for detailed interface information and timing parameters). Each
MII port has the following characteristics:
Capable of supporting both 10 Mbps and 100 Mbps data rates in half or full duplex modes
Data and delimiters are synchronous to clock references
Provides independent 4-bit wide transmit and receive paths
Uses TTL signal levels
Provides a simple management interface (common to all ports)
Capable of driving a limited length of shielded cable
The GT-48006A incorporates all the required digital circuitry to interface to 100BaseTX, 100BaseT4, and 100BaseFX.
9.1
10/100 MII Compatible Interface
The GT-48006A MAC allows it to be connected to a 10Mbps or 100Mbps network. The GT-48006A interfaces to an
IEEE 802.3u 10/100 Mbps MII compatible PHY device. The data path consists of a separate nibble-wide stream for
both transmit and receive data. The GT-48006A can switch automatically between 10 or 100 Mbps operation depend-
ing on the speed of the network. Data transfers are clocked by the 25 MHz transmit and receive clocks in 100 Mbps
operation, or by 2.5 MHz transmit and receive clocks in 10 Mbps operation. The clock inputs are driven by the PHY,
which controls the clock rate based on auto-negotiation.
9.2
Media Access Control (MAC)
The GT-48006A MAC performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, col-
lision handling, deferral to link traffic, etc. The GT-48006A ensures that any outgoing packet complies with the 802.3
specification in terms of preamble structure. The GT-48006A transmits 56 preamble bits before Start of Frame Delim-
iter (SFD). The GT-48006A operates in half-duplex or full-duplex modes. In half-duplex mode, the GT-48006A checks
that there is no competitor for the network bus before transmission. In addition to listening for a clear line before trans-
mitting, the GT-48006A handles collisions in a pre-determined way. If two nodes attempt to transmit at the same time,
the signals collide and the data on the line is garbled. The GT-48006A listens while it is transmitting, and it can detect a
collision. If a collision is detected, the GT-48006A transmits a ‘JAM’ pattern and then delays its re-transmission for a
random time period determined by the backoff algorithm. In full-duplex mode, the GT-48006A transmits unconditionally.
9.3
Auto-negotiation
9.3.1
Disabled
Autonegotiation can be disabled for a port through the state of the DAddr[1:0] pins at reset. Following RESET the port
duplex mode is set by the state sampled on DAddr[6] for Port 0 and DAddr[7] for Port 1. The speed that each port oper-
ates in (10Mbps or 100Mbps) is determined by the frequency of TxClk[x] and RxClk[x] generated by the PHY. When the
port is operating at 10Mbps, the PHY generates a 2.5MHz clock for both TxClk and RxClk. When the port is operating
at 100Mbps, the PHY generates a 25MHz clock for both TxClk and RxClk.
9.3.2
Enabled
When auto-negotiation is enabled for a port the GT-48006A decodes the duplex mode for each port from the values of
the Auto-Negotiation Advertisement register and the Auto-Negotiation Link Partner Ability registers at the end of the
Auto-Negotiation process.
Note: If autonegotiation is enabled for either port, then the link status for BOTH ports will be determined auto-
matically by the GT-48006A by reading the PHY status registers. FORCE LINK PASS overrides the PHY in this
mode.
The auto-negotiation feature on the GT-48006A is used only to tell the GT-48006A the duplex status of each port. The
speed (10/100) of each port is determined only by RxClk and TxClk. The GT-48006A will continuously perform the fol-
lowing operations for each port (PHY addresses 1 and 2 alternately), implemented as READ commands issued via the
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