參數(shù)資料
型號(hào)： GT-48006A
廠商： Galileo Technology Services, LLC
英文描述： Low Cost Two Port 10/100Mbps Ethernet Bridge/Switch Controller(低成本、雙端口10/100Mbps以太網(wǎng)橋式/交換式控制器)
中文描述： 低成本雙口10/100Mbps以太網(wǎng)橋/開(kāi)關(guān)控制器（低成本，雙端口10/100以太網(wǎng)橋式/交換式控制器）
文件頁(yè)數(shù)： 8/33頁(yè)
文件大?。?/td> 352K
代理商： GT-48006A
GT-48006A Low Cost Two Port 10/100 Ethernet Bridge/Switch Controller
16
9.5
Data Blinder
The internal data blinder field sets the period of time during which the port does not look at the wire to decide to trans-
mit (inhibit time.) The value is fixed at 32 bit times.
9.6
Inter-Packet Gap (IPG)
IPG is the idle time between any two successive packets from the same port. The value (from the standard) is 9.6uS for
10Mbps Ethernet and 960nsec for 100-Mbps Fast Ethernet.
9.7
10/100 Mbps MII Transmission (Half-Duplex)
When the GT-48006A has a frame ready for transmission, it samples the link activity. If the RxDV signal is inactive (no
activity on the link), and the Inter-packet gap (IPG) counter has expired, frame transmission begins. The data is trans-
mitted via pins TxD[3:0] of the transmitting port, clocked on the rising edge of TxClk. The signal TxEn is asserted at this
same time. In the case of collision, the PHY asserts the CoL signal on the GT-48006A which will then stop transmitting
the frame and transmit a jam sequence onto the link. After the end of a collided transmission, the GT-48006A will back
off and attempt to retransmit once the backoff counter expires.
A waveform of the signals which are synchronous to TxClk (TxD0[3:0], TxD1[3:0], TxEn[1:0]) is shown in Figure 2. The
actual delay times of the GT-48006A are tighter than the IEEE 802.3u standard, clause 22.3.1, as shown in Table 3.
Figure 2: MII Transmit Signal Timing
Table 3: MII Signal Timings Synchronous to TxClk
9.8
10/100 Mbps MII Reception (Half-Duplex)
Frame reception starts with the assertion of RxDV (while the GT-48006A is not transmitting) by the PHY. Once RxDV is
asserted, the GT-48006A will begin sampling incoming data on pins RxDV[3:0] on the rising edge of RxClk. Reception
ends when the RxDV is deasserted by the PHY. The last nibble sampled by the GT-48006A is the nibble present on
RxD[3:0] on the last RxClk rising edge in which RxDV is still asserted. During reception, the RxDV is asserted. If, while
RxDV is asserted, the GT-48006A detects the assertion of RxEr, it will designate this packet as corrupted. While no
reception is taking place, RxDV should remain deasserted.
A waveform of the signals which are synchronous to RxClk (RxD0[3:0], RxD1[3:0], RxDV[1:0], RxEr[1:0]) is shown in
Figure 3. The setup and hold times of the GT-48006A are tighter than the IEEE 802.3u standard, clause 22.3.2, as
shown in Table 4.
GT-48006A
I E E E 80 2 . 3u S p ec .
Na m e
Pa ra m e te r
MI N
MAX
MI N
MAX
Un its
vd
Valid Delay after Rising TxClk
2
14
0
25
ns
vd
TxClk
TxD, TxEn
Vih
min
Vil
max
Vih
min
Vil
max
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