參數(shù)資料
型號(hào): GT28F320D18B110
英文描述: x16 Flash EEPROM
中文描述: x16閃存EEPROM
文件頁(yè)數(shù): 26/83頁(yè)
文件大小: 836K
代理商: GT28F320D18B110
28F320D18
22
Product Preview
0672_05
4.10.3
Data Output Configuration
The output configuration determines the number of clocks that data will be held valid. The data
hold time for the 1.8 V Dual-Plane Flash memory is one clock.
0672_06
4.10.4
WAIT# Configuration
The WAIT# configuration bit controls the behavior of the WAIT# output signal. This output signal
can be set to be asserted during or one CLK cycle before an output delay when continuous burst
length is enabled. Its setting will depend on the system and CPU characteristic. WAIT# can also be
asserted in the 4- or 8-word burst length when RCR.3 = 1 (no-wrap mode) if the no-wrap read
crosses the first 16-word boundary.
4.10.5
Burst Sequence
The burst sequence specifies the order in which data is addressed in synchronous burst mode. This
order is programmable as either linear or Intel burst order. The continuous burst length only
supports linear burst order. The order chosen will depend on the CPU characteristic. See
Table 10,
“Sequence and Burst Length” on page 23
for more details.
Figure 5. Frequency Configuration
ADV# (V)
A
20-0
(A)
Valid
Address
CLK (C)
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Code 3
Code 4
Figure 6. Output Configuration
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
CLK (C)
1 CLK
Data Hold
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