參數(shù)資料
型號(hào)： GT28F320D18B110
英文描述： x16 Flash EEPROM
中文描述： x16閃存EEPROM
文件頁(yè)數(shù)： 54/83頁(yè)
文件大?。?/td> 836K
代理商： GT28F320D18B110
28F320D18
50
Product Preview
this is the worst case delay. The delay will only take place once during a continuous burst access,
and if the burst sequence never crosses a 16-word boundary, the delay will never happen. When the
output delay is encountered, the WAIT# pin will be asserted. This signal should be fed into the
systems wait-state control logic or directly to the CPU.
The WAIT# output pin is gated by OE# and CE#. If either OE# or CE# go inactive, the WAIT#
output buffer turns off. An internal pull-up resistor holds WAIT# at a logic ’1’ state. The resistor
value is approximately 1 M
. This output configuration allows multiple banks of flash enable wire
ORing, as shown in
Figure 15, “WAIT# Pin Connection Using Multiple Flash Memory
Components” on page 45
. WAIT# can also be configured for a couple different characteristics to
help simplify system usage. It can be configured for assertion during the delay or one data cycle
before the delay.
7.3.7
Write Operations
Write operations are used to switch the memory device between modes, to initiate a program or
erase, to lock or unlock blocks, and to write memory to the device to be stored. Commands that
switch modes of the device or suspend/resume a program or erase take one write cycle. Commands
which initiate a program or erase or lock/unlock blocks take two write cycles. A program command
is required before each data word to be programmed into the flash device, even if multiple data
words are programmed back to back.
Write operations transpire as asynchronous operations, similar to other Intel Flash memory
families, such as Advanced or Advanced+ Boot Block and Fast Boot Block memory. The flash
memory latches the address during writes the same way as during reads. The data, as in all Intel
Flash memory components, is latched on the rising edge of CE# or WE#, whichever goes high first.
For a write cycle, WE# and CE# are interchangeable.
After completing a program or erase or program/erase suspend command, the flash device
automatically goes into read status mode. Any reads to the flash at this point will return status
register data. This data is not updated to the output pins continually, rather CE# and/or OE# need to
be toggled for updated status register data. After a Set Read Configuration Register command, the
flash device goes into read array mode.
7.4
Design Tools and Software
7.4.1
Design Tools
Several tools are available which will simplify designing in 1.8 Volt Dual-Plane Flash memory
components into a system. They include VHDL and Verilog bus functional models, Timing
Designer* files, and IBIS files. Some of these tools can be found on Intel’s website, otherwise they
can be obtained by contacting an Intel field representative. Visit http://developer.intel.com/design/
flash/swtools/ for more details.
7.4.2
Flash Data Integrator (FDI)
Intel
Flash Data Integrator software is a code plus data storage manager for use in real-time
embedded applications. This software enables code execution and data storage in a single flash
device. It handles parameter, data-stream, and packet storage, as well as sophisticated file-system
features like wear-leveling, power-loss recovery and block reclaims. By consolidating code and
data storage in a single flash device, FDI reduces component count, allowing decreases in board
相關(guān)PDF資料
PDF描述
GT28F320D18B120 x16 Flash EEPROM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GT28F320D18B120 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 Flash EEPROM
GT28F320S3-100 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile⑩ MEMORY FAMILY
GT28F320S3-120 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY
GT28F320W18BC60 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory
GT28F320W18BC80 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory
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