參數(shù)資料
型號： HC05PL4GRS
英文描述： 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification
中文描述： 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范
文件頁數(shù)： 12/98頁
文件大小： 1004K
代理商： HC05PL4GRS
GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
1-2
GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
MC68HC05PL4
REV 2.0
1.2
MCU BLOCK DIAGRAM
Figure 1-1. MC68HC05PL4 Block Diagram
NOTE
A line over a signal name indicates an active low signal. Any reference to voltage,
current, or frequency specified in the following sections will refer to the nominal
values. The exact values and their tolerance or limits are specified in Electrical
Specifications section.
USER ROM - 4k BYTES
USER RAM - 256 BYTES
ACCUMULATOR
INDEX REGISTER
5
1
STACK POINTER
4
PROGRAM COUNTER
7
CONDITION CODE REGISTER
M68HC05
CPU
RESET
0
12
0
1
1 H I N Z C
OSC
POWER
OSC1
OSC2
VDD
VSS
D
P
PB4- PB7
4
1 1
7
0
7
0
0
0
0
0
0
15
0
D
P
KEYBOARD
INTERRUPT
WATCHDOG
SYSTEM
PA6
PA5
PA4
PA3/TCMP
PA2/TCAP
PA1/DTMF
PA0
4
16-BIT
PROGRAMMABLE TIMER
VERY LOW
FREQUENCY OSC
(RC: 500kHz or 20kHz)
(
÷
N OPTIONAL)
DTMF
MODULE
LED/IRQ
LED
DRIVE
D
P
PC0 - PC7
8
8-BIT RELOADABLE
EVENT TIMER
PB0/KBI0
PB1/KBI1
PB2/KBI2
PB3/KBI3
Available on MC68HC05PL4B only.
Available on MC68HC05PL4 only.
F
Freescale Semiconductor, Inc.
n
.
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