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| 型號： | HC05PL4GRS |
| 英文描述： | 68HC05PL4A. 68HC05PL4B. 68HC705PL4B General Release Specification |
| 中文描述： | 68HC05PL4A。 68HC05PL4B。 68HC705PL4B一般版本規(guī)范 |
| 文件頁數(shù)： | 34/98頁 |
| 文件大小： | 1004K |
| 代理商： | HC05PL4GRS |
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GENERAL RELEASE SPECIFICATION
April 30, 1998
MOTOROLA
5-2
RESETS
MC68HC05PL4
REV 2.0
A 4064 t
CYC
(internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If the RESET pin is at logic zero at the end of the
multiple t
CYC
time, the MCU remains in the reset condition until the signal on the
RESET pin goes to a logic one.
POR - Power on Reset Flag
The POR bit is set each time the device is powered on. It allows the user to
make a software distinction between a power-on and an external reset. POR
can be cleared by software by writing a ‘0’ to the bit. It cannot be set by soft-
ware.
5.2
EXTERNAL RESET
A logic zero applied to the RESET pin for 1.5t
CYC
generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. The external
reset occurs whenever the RESET pin is pulled below the lower threshold and
remains in reset until the RESET pin rises above the upper threshold. This active
low input will generate the internal RST signal that resets the CPU and peripher-
als.
The RESET pin can also act as an open drain output. It will be pulled to a low
state by an internal pulldown device that is activated by three internal reset
sources. This RESET pulldown device will only be asserted for 3-4 cycles of the
internal clock, f
OP
, or as long as the internal reset source is asserted. When the
external RESET pin is asserted, the pulldown device will not be turned on.
NOTE
Do not connect the RESET pin directly to V
DD
, as this may overload some power
supply designs when the internal pulldown on the RESET pin activates.
5.3
INTERNAL RESETS
The four internally generated resets are the initial power-on reset function, the
COP Watchdog timer reset, the low voltage reset, and the illegal address detector.
Only the COP Watchdog timer reset, low voltage reset and illegal address detec-
tor will also assert the pulldown device on the RESET pin for the duration of the
reset function or 3-4 internal clock cycles, whichever is longer.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MICSR
$001C
RESET
R
W
IRQEN
IRQS
TCMPEN
TCAPEN
LED
COPON
POR
0
0
0
0
0
0
0
0
Figure 5-2. Miscellaneous Control and Status Register (MICSR)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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